Flag fault-tolerant error correction with arbitrary distance codes

ABSTRACT

Fault-tolerant error correction (EC) is desirable for performing large quantum computations. In this disclosure, example fault-tolerant EC protocols are disclosed that use flag circuits, which signal when errors resulting from υ faults have weight greater than υ. Also disclosed are general constructions for these circuits (also referred to as flag qubits) for measuring arbitrary weight stabilizers. The example flag EC protocol is applicable to stabilizer codes of arbitrary distance that satisfy a set of conditions and uses fewer qubits than other schemes, such as Shor, Steane and Knill error correction. Also disclosed are examples of infinite code families that satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Using fewer resources than Shor EC, the example flag EC protocols can be used in low-overhead fault-tolerant EC protocols using large low density parity check quantum codes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/541,902, filed on Aug. 7, 2017, and entitled “FLAG FAULT-TOLERANTERROR CORRECTION WITH ARBITRARY DISTANCE CODES,” which is herebyincorporated herein by reference in its entirety.

SUMMARY

Fault-tolerant error correction (EC) is desirable for performing largequantum computations. In this disclosure, example fault-tolerant ECprotocols are disclosed that use flag circuits, which signal when errorsresulting from υ faults have weight greater than υ. Also disclosed aregeneral constructions for these circuits (also referred to as flagqubits) for measuring arbitrary weight stabilizers. The example flag ECprotocol is applicable to stabilizer codes of arbitrary distance thatsatisfy a set of conditions and uses fewer qubits than other schemes,such as Shor, Steane and Knill error correction. Also disclosed areexamples of infinite code families that satisfy these conditions andanalyze the behaviour of distance-three and -five examples numerically.Using fewer resources than Shor EC, the example flag EC protocols can beused in low-overhead fault-tolerant EC protocols using large low densityparity check quantum codes.

In some embodiments, a quantum operation is performed in a quantumcircuit implemented in the quantum computing device, and afault-tolerant error correction protocol is performed using only asingle ancilla qubit and an error-code distance of 3. In particularimplementations, the fault-tolerant error correction protocol performssyndrome measurements at most three times. In some implementations, theperforming the fault-tolerant error correction protocol comprisesrepeating an error syndrome measurement of the ancilla qubit until oneof multiple criteria is satisfied.

In further embodiments, a quantum operation is performed in a quantumcircuit implemented in the quantum computing device; and afault-tolerant error correction protocol is performed using only twoancilla qubits and an error-code distance of 5. In particularimplementations, the fault-tolerant error correction protocol performssyndrome measurements at most seven times. In certain implementations,the performing the fault-tolerant error correction protocol comprisesrepeating error syndrome measurements of the two ancilla qubits untilone of multiple criteria is satisfied. In some implementations, theperforming the fault-tolerant error correction protocol furthercomprises tracking a number of times consecutive measurements aredifferent and a number of times consecutive measurements are equal.

In some embodiments, a quantum operation is performed in a quantumcircuit implemented in the quantum computing device; and afault-tolerant error correction protocol is performed using one or morequbits and stabilizer codes of an arbitrary distance. In someimplementations, the performing the fault-tolerant error correctionprotocol further comprises tracking a number of times consecutivemeasurements of the one or more qubits are different and a number oftimes consecutive measurements of the one or more qubits are equal.

The disclosed methods can be implemented, at least in part, ascomputer-executable instructions (software) stored on one or morecomputer-readable media (storage devices or memory devices) andexecutable by one or more processors. The processors can be classicalcomputer processors that are used as part of the system that controls,monitors, and/or reads out results from a quantum device (e.g., aquantum computer).

The foregoing and other objects, features, and advantages of theinvention will become more apparent from the following detaileddescription, which proceeds with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application publication withcolor drawing(s) will be provided by the Office upon request and paymentof the necessary fee.

FIG. 1 is a schematic block diagram illustrating s faults as occurringduring a round of error correction by a vertical arrow, and an incomingstate a distance r from the desired codeword by a horizontal arrow withr above.

FIG. 2(a) is a schematic block diagram showing a non-fault-tolerantcircuit. A single fault IZ occurring on the third CNOT (from the left)results in the bad error IIZZ on the data block. FIG. 2(b) is aschematic block diagram showing a flag version of FIG. 2(a). FIG. 2(c)is a schematic block diagram showing an alternative flag circuit with adifferent set of bad errors and lower depth than FIG. 2(b).

FIG. 3 is a schematic block diagram showing a tree diagram illustratingthe possible paths of the Flag 1-FTEC Protocol.

FIG. 4(a) is a schematic block diagram showing a representation of theSteane code where each circle is a qubit, and there is an X- and aZ-type stabilizer generator for each face. FIG. 4(b) is a schematicblock diagram where only Z error contributions are shown.

FIG. 5 is a schematic block diagram showing a tree diagram for the Flag2-FTEC protocol.

FIG. 6(a) shows a schematic block diagram of a 19-qubit 2D color code,and FIG. 6(b) shows a schematic block diagram of a 17-qubit 2D colorcode.

FIG. 7 illustrates 2-flag circuits with minimal number of flag qubitsand CNOT's. In particular, FIG. 7(a) is a schematic block diagramshowing a circuit for measuring the Pauli Z^(⊗6) using 2 flag qubits,and FIG. 7(b) is a schematic block diagram of a circuit for measuringthe the Pauli Z^(⊗8).

FIG. 8(a) is a schematic block diagram illustrating a general 1-flagcircuit construction for measuring the stabilizer Z^(⊗w) which requiresonly two CNOT_(fm) gates. FIG. 8(b) is a schematic block diagramillustrating a general 2-flag circuit construction of the circuit ofFIG. 8(a). FIG. 8(c) is a schematic block diagram illustrating that itis possible to reuse some flag qubits to measure multiple pairs ofCNOT_(fm) gates at the cost of introducing extra time steps into thecircuit.

FIGS. 9(a) and 9(b) are schematic block diagrams showing that flagcircuits can use more than one flag qubit.

FIG. 10 is a schematic block diagram illustrating an example d=5 rotatedsurface code.

FIG. 11 is a graph showing the logical failure rates of the

19, 1, 5

color code after performing a round of flag EC presented in Section IIIB for the three noise models described in Section II B.

FIG. 12 is a diagram showing graphs 12(a)-(f) for the logical failurerates for various error correction methods, including variousfault-tolerant error correction methods applied to the

5, 1, 3

code,

7, 1, 3

Steane code and the

19, 1, 5

color code.

FIG. 13(a) is a schematic block diagram showing a fault-tolerant Steaneerror correction circuit which can be applied to CSS codes. FIG. 13(b)is a schematic block diagram showing a fault-tolerant Steane errorcorrection circuit which can be used for any CSS stabilizer codeencoding the data.

FIG. 14(a) is a schematic block diagram illustrating a situation whereresting qubits are chosen to fail with a total probability {tilde over(p)}=p. FIG. 14(b) is a schematic block diagram illustrating a situationwhere resting qubits fail with probability {tilde over (p)}=p/100. Theintersection between the dashed curve and solid lines represent thepseudo-threshold of both error correction schemes.

FIG. 15 is a schematic block diagram illustrating a situation where therotated surface code has n=d² data qubits for distance d.

FIG. 16(a) is a schematic block diagram showing a Z-type generator. FIG.16(b) is a schematic block diagram showing an X-type generator.

FIG. 17(a) illustrates a situation where an X error occurs during thethird time step in the CNOT gate acting on the central data qubit. FIG.17(b) illustrates that during the fifth time step of this round, the Xerror is detected by the Z type measurement qubit to the top right. FIG.17(c) illustrates that the X error is not detected by the bottom left Ztype stabilizer until the following round. FIG. 17(d) illustrates thatan XX error occurs on the third CNOT of an X measurement circuit, whichis detected by the Z measurement to the right. FIG. 17(e) illustratesthat detection by the left Z stabilizer does not occur until the nextround. FIG. 17(f) illustrates that the corresponding edges in G_(3D),green for (a-c), and blue for (d-e). Here, it is shown that two roundsof the graph ignoring boundary edges.

FIG. 18 is a schematic block diagram illustrating a circuit formeasuring the Z stabilizer generators of the

7, 1, 3

code using one flag qubit and three measurement qubits.

FIG. 19 is a graph showing logical failure rates of flag-EC protocolsusing two and four ancilla qubits applied to the

7, 1, 3

Steane code.

FIG. 20 illustrates a generalized example of a suitable computingenvironment in which several of the described embodiments can beimplemented.

FIG. 21 is a schematic block diagram showing an example of a possiblenetwork topology (e.g., a client-server network) for implementing asystem according to the disclosed technology.

FIG. 22 is a schematic block diagram showing another example of apossible network topology for implementing a system according to thedisclosed technology.

FIG. 23 is a schematic block diagram of an exemplary system forimplementing the disclosed technology using a quantum computing deviceand a classical computer.

FIG. 24 is an example flow chart for applying aspects of the disclosedtechnology.

FIG. 25 is a flowchart illustrating a technique for implementing anerror correction protocol in a quantum computing device in accordancewith embodiments of the disclosed technology.

FIG. 26 is a flowchart illustrating another technique for implementingan error correction protocol in a quantum computing device in accordancewith embodiments of the disclosed technology.

FIG. 27 is a flowchart illustrating a further technique for implementingan error correction protocol in a quantum computing device in accordancewith embodiments of the disclosed technology.

DETAILED DESCRIPTION I. General Considerations

As used in this application, the singular forms “a,” “an,” and “the”include the plural forms unless the context clearly dictates otherwise.Additionally, the term “includes” means “comprises.” Further, as usedherein, the term “and/or” means any one item or combination of any itemsin the phrase.

Although the operations of some of the disclosed methods are describedin a particular, sequential order for convenient presentation, it shouldbe understood that this manner of description encompasses rearrangement,unless a particular ordering is required by specific language set forthbelow. For example, operations described sequentially may in some casesbe rearranged or performed concurrently. Moreover, for the sake ofsimplicity, the attached figures may not show the various ways in whichthe disclosed systems, methods, and apparatus can be used in conjunctionwith other systems, methods, and apparatus. Additionally, thedescription sometimes uses terms like “produce” and “provide” todescribe the disclosed methods. These terms are high-level abstractionsof the actual operations that are performed. The actual operations thatcorrespond to these terms will vary depending on the particularimplementation and are readily discernible by one of ordinary skill inthe art.

II. Introduction and Formalism

The field of quantum computing has made significant recent progress.However, no practical model for a self-correcting quantum memory hasbeen disclosed to date, despite considerable effort. See, e.g., B. J.Brown et al., “Quantum memories at finite temperature,” Rev. Mod. Phys.,vol. 88, p. 045005, November 2016. The models that come closest to thisgoal involve topological protection in the presence of physicallyimposed symmetries, but even these are not expected to reduce errorrates sufficiently for large computations. See, e.g., A. Y. Kitaev,“Unpaired majorana fermions in quantum wires,” Physics-Uspekhi, vol. 44,no. 10S, p. 131, 2001; T. Karzig et al., “Scalable designs forquasiparticle-poisoning-protected topological quantum computation withmajorana zero modes,” Phys. Rev. B, vol. 95, p. 235305, June 2017.Therefore active protocols that measure the check operators of an errorcorrecting code are desirable to realize scalable quantum computing.

Fortunately, there are three general approaches of fault-tolerant errorcorrection (EC) applicable to a wide range of stabilizer codes due toShor, Steane, and Knill. See P. W. Shor, “Fault-tolerant quantumcomputation,” Proceedings, 37th Annual Symposium on Foundations ofComputer Science, pp. 56-65 (1996); A. W. Steane, “Active stabilization,quantum computation, and quantum state synthesis,” Phys. Rev. Lett.,vol. 78, no. 11, p. 2252, 1997; and E. Knill, “Scalable quantumcomputing in the presence of large detected-error rates,” Phys. Rev. A,vol. 71, p. 042322 (2005). Along with the ability to prepare, measureand perform gates on states fault-tolerantly, fault-tolerant EC (FTEC)gives rise to the threshold theorem. The threshold theorem guaranteesthat arbitrarily long quantum computations can be performed witharbitrarily small failure probability with poly-logarithmic overheadprovided the noise is below some threshold. See, e.g., P. W. Shor,“Fault-tolerant quantum computation,” Proceedings, 37th Annual Symposiumon Foundations of Computer Science, pp. 56-65 (1996); D. Aharonov and M.Ben-Or, “Fault-tolerant quantum computation with constant error,” inProceedings of the twenty-ninth annual ACM symposium on Theory ofcomputing, pp. 176-188, ACM (1997); J. Preskill, “Reliable quantumcomputers,” Proceedings of the Royal Society of London. Series A:Mathematical, Physical and Engineering Sciences, vol. 454, no. 1969, pp.385-410 (1998); E. Knill et al., “States, effect, and operations,”Science, vol. 279, pp. 342-345 (1998).

Shor EC can be applied to any stabilizer code, but typically requiresmore syndrome measurement repetitions than Steane and Knill EC. Weight-wstabilizer generators are measured sequentially using w-qubit verifiedcat states. On the other hand, Steane EC has higher thresholds than ShorEC and has the advantage that all Clifford gates are appliedtransversally during the protocol. However, Steane EC is only applicableto CSS codes and uses a verified logical |+

state encoded in the same code to simultaneously obtain all X-typesyndromes, using transverse measurement (similarly for Z). See A. R.Calderbank and P. W. Shor, “Good quantum error-correcting codes exist,”Phys. Rev. A, vol. 54, pp. 1098-1105 (1996). Knill EC can also beapplied to any stabilizer code but requires the preparation of a logicalBell state using the same code used to protect the data. The Bell stateis used to teleport the encoded information to a code block and theextra information from the transversal Bell measurement gives the errorsyndrome. Knill EC typically achieves higher thresholds than Shor andSteane EC but often uses more qubits. See E. Knill, “Quantum computingwith realistically noisy devices,” Nature, vol. 434, no. 7029, pp. 39-44(2005); J. Fern, “An upper bound on quantum fault tolerant thresholds,”arXiv:quant-ph/0801.2608 (2008).

A promising FTEC approach which does not fit into the above schemes isto use the surface code with a minimum weight matching error correctionscheme. This approach gives the best fault-tolerant thresholds to dateusing only geometrically local measurements.

However there are reasons to believe that there could be betterapproaches than the surface code. For example, dramatically improvedthresholds could be possible using Steane or Knill EC with concatenatedcodes if they enjoyed the same level of optimization as the surface codehas in recent years. See D. Poulin, “Optimal and efficient decoding ofconcatenated quantum block codes,” Phys. Rev. A., vol. 74, p. 052333(2006). Another enticing alternative is to use large, high-rate,efficiently decodable low density parity check (LDPC) codes in alow-overhead FTEC protocol. See R. G. Gallager, “Low density paritycheck codes,” PhD thesis, MIT (1960); A. A. Kovalev et al., “Faulttolerance of quantum low-density parity check codes with sublineardistance scaling,” Phys. Rev. A, vol. 87, p. 020304 (February 2013); andD. Gottesman, “Fault-tolerant quantum computation with constantoverhead,” arXiv:quant-ph/1310.2984 (2013). It is noteworthy that forlarge LDPC codes, in which low weight generators should befault-tolerantly measured, Shor EC is much more favorable than Steane orKnill EC.

In this disclosure, embodiments are presented that significantly buildon some recent work that demonstrate flag error correction forparticular distance three codes. See, e.g., R. Chao and B. W. Reichardt,“Quantum error correction with only two extra qubits,”arXiv:quant-ph/1705.02329 (2017); R. Chao and B. W. Reichardt,“Fault-tolerant quantum computation with few qubits,”arXiv:quant-ph/1705.05365 (2017); and T. J. Yoder and I. H. Kim, “Thesurface code with a twist,” Quantum, vol. 1, p. 2 (April 2017). Further,the disclosed technology includes a general protocol for arbitrarydistance codes. Among the issues discussed herein is the extension ofthe lifetime of encoded information using fault-tolerant errorcorrection. Also disclosed herein is a set of example requirements for astabilizer code (along with the circuits used to measure thestabilizers) which, if satisfied, can be used for flag error correction.Embodiments of the disclosed approach can be applied to a broad class ofcodes (including but not limited to surface codes, color codes, andquantum Reed-Muller codes).

There are a number of potential applications of these results. Firstly,it is advantageous to have new EC schemes with different properties thatcan be used in various settings. Secondly, flag EC involves very smallqubit overhead, hence the schemes presented here will find applicationsin early qubit-limited experiments. Thirdly, the flag error correctionprotocol presented here is useful for LDPC codes as described in D.Gottesman, “Fault-tolerant quantum computation with constant overhead,”arXiv:quant-ph/1310.2984 (2013). This is because flag error correctionrequires fewer resources than Shor EC (it uses fewer qubits, fewerrounds, and does not require verified state preparation).

In Sections III A and III B, definitions are provided flag FTEC isintroduced for distance-three and -five codes. In Section III C, anexample of the protocol is applied to two examples: the

19, 1, 5

and

17, 1, 5

color codes, which importantly have a variety of different weightstabilizers. The general flag FTEC protocol for arbitrary distance codesis given in Section IV A followed by flag circuit constructions formeasuring arbitrary weight stabilizers in Section IV B. In Section IV C,examples are provided of codes that satisfy the conditions that are usedfor flag FTEC. In Section V, a numerical analysis is provided for anumber of flag EC schemes and compared with other FTEC schemes undervarious types of circuit level noise. As discussed herein, it has beenfound that flag EC schemes, which have large numbers of idle qubitlocations, behave best in error models in which idle qubit errors occurwith a lower probability than CNOT errors. The remainder of this sectionis devoted to FTEC and noise model/simulation methods.

A. Fault-Tolerant Error Correction

Throughout this disclosure, a simple depolarizing noise model is assumedin which idle qubits fail with probability {tilde over (p)} and allother circuit operations (gates, preparations and measurements) failwith probability p, which recovers standard circuit noise when {tildeover (p)}=p. A detailed description is given in Section II B.

The weight of a Pauli operator is the number of qubits on which it hasnon-trivial support. The following set is first defined:

Definition 1. Weight-t Pauli OperatorsE _(t)={E∈

_(n)|wt(E)≤t},   (1)where

_(n) is the n-qubit Pauli group.

An error correction protocol typically comprises a sequence of basicoperations to infer syndrome measurements of a stabilizer code C,followed by the application of a Pauli operator (either directly orthrough Pauli frame tracking intended to correct errors in the system).See D. P. DiVincenzo and P. Aliferis, “Effective fault-tolerant quantumcomputation with slow measurements,” Phys. Rev. Lett., vol. 98, p.020501 (2007); C. Chamberland et al., “Fault-tolerant quantum computingin the pauli or clifford frame with slow error diagnostics,”arXiv:quant-ph/1704.06662 (2017). A given protocol is fault-tolerant iffor sufficiently weak noise, the effective noise on the logical qubitsis even weaker. More precisely, one can say that an error correctionprotocol is a t-FTEC if the following is satisfied:

Definition 2. Fault-Tolerant Error Correction

For t=└(d−1)/2┘, an error correction protocol using a distance-dstabilizer code C is t-fault-tolerant if the following two conditionsare satisfied:

-   -   1. For an input codeword with error of weight s₁, if s₂ faults        occur during the protocol with s₁+s₂≤t, ideally decoding the        output state gives the same codeword as ideally decoding the        input state.    -   2. For s faults during the protocol with s≤t, then no matter how        many errors are present in the input state, the output state        differs from a valid codeword by an error of at most weight s.

Here ideally decoding is equivalent to performing fault-free errorcorrection. By valid codeword, any state |ψ

∈C such that g|ψ

=|ψ

∀g∈S where S is the stabilizer group for the code C is meant. Note thatfor the second criteria in Definition 2, the output and input codewordcan differ by a logical operator.

The first criteria in Definition 2 ensures that correctable errors donot spread to uncorrectable errors during the error correction protocol(the output state can differ from the input codeword by an error ofweight at most s₁+s₂). Further, if s₂=0 then all errors present in theinput state will be removed.

The second condition is not always checked for protocols in theliterature, but it is believed it is important as it ensures that errorsdo not accumulate uncontrollably in consecutive rounds of errorcorrection (see schematic block diagram 100 of FIG. 1). To see why thisis, consider a scenario with s faults introduced during each round oferror correction, and assume that t/n<s<(2t+1)/3 for some integer n. Thefirst condition alone implies that an input state E₁|ψ

with wt(E₁)≤s is taken to E₂|ψ

, with wt(E₂)≤2s by one error correction round with s faults. After thejth round, the state will be E_(j)|ψ

with the first condition implying wt(E_(j))≤j·s provided that j≤n.However, when j>n, the requirement of the first condition is no longersatisfied so one cannot use it to upper bound wt(E_(j)). Now considerthe same scenario but assuming both conditions hold. The secondcondition implies that after the first round, the input state E₁|ψ

becomes E′₂|ϕ

=E₂|ψ

, with wt(E′₂)≤s, and where |ϕ

is a codeword. Therefore the codewords are related by: |ϕ

=(E′^(†) ₂E₂)|ψ

, with logical operator (E′^(†) ₂E₂) having weight at most 3s, sincewt(E₂)+wt(E′₂)≤3s. However, the minimum non-trivial logical operator ofthe code has weight (2t+1)>3s, implying that |ψ

=|ϕ

, and therefore that wt(E₂)=wt(E′₂)≤s. Hence, for the jth round,wt(E_(j))≤s for all j, e.g. the distance from the codeword is notincreased by consecutive error correction rounds with s faults, provideds<(2t+1)/3.

In schematic block diagram 100 of FIG. 1, s faults are represented asoccurring during a round of error correction by a vertical arrow, and anincoming state a distance r from the desired codeword by a horizontalarrow with r above. Both fault tolerance conditions in Definition 2 areused together to imply a long lifetime of encoded information. The firstcondition alone allows errors to build up over time as in the topportion of FIG. 1, which would quickly lead to a failure. Howeverprovided s<(2t+1)/3, both conditions together ensure that errors inconsecutive error correction rounds do not build up, provided each errorcorrection round introduces no more than s faults, which could remaintrue for a long time.

B. Noise Model and Pseudo-Threshold Calculations

In Section V, a full circuit level noise analysis is performed ofvarious error correction protocols. Unless otherwise stated, thefollowing depolarizing noise model is used:

-   -   1. With probability p, each two-qubit gate is followed by a        two-qubit Pauli error drawn uniformly and independently from {I,        X, Y, Z}^(⊗2)\{I⊗I}.    -   2. With probability

$\frac{2\; p}{3},$the preparation of the |0

state is replaced by |1

=X|0

. Similarly, with probability

$\frac{2\; p}{3},$the preparation of the |+

state is replaced by |−

=Z|+

.

-   -   3. With probability

$\frac{2\; p}{3},$any single qubit measurement has its outcome flipped.

-   -   4. Lastly, with probability {tilde over (p)}, each resting qubit        location is followed by a Pauli error drawn uniformly and        independently from {X, Y, Z}.

Some error correction schemes that are analyzed contain a significantnumber of idle qubit locations. Consequently, most schemes will beanalyzed using three ratios ({tilde over (p)}=p, {tilde over (p)}=p/10and {tilde over (p)}=p/100) to highlight the impact of idle qubitlocations on the logical failure rate.

The two-qubit gates considered are: CNOT, XNOT=H₁(CNOT)H₁, andCZ=H₂(CNOT)H₂.

Logical failure rates are estimated using an N-run Monte Carlosimulation. During a particular run, errors are added at each locationfollowing the noise model described above. Once the error locations arefixed, the errors are propagated through a fault-tolerant errorcorrection circuit and a recovery operation is applied. After performinga correction, the output is ideally decoded to verify if a logical faultoccurred. For an error correction protocol implemented using astabilizer code C and a fixed value of p, one can define the logicalfailure rate

$\begin{matrix}{{{p_{L}^{(C)}(p)} = {\lim\limits_{N\rightarrow\infty}\frac{N_{fail}^{(C)}(p)}{N}}},} & (2)\end{matrix}$where N^((C)) _(fail)(p) is the number of times a logical X or logical Zerror occurred during the N rounds. In practice, one takes Nsufficiently large to estimate p^((C)) _(L)(p), and provide error bars.See P. Aliferis and A. Cross, “Subsystem fault tolerance with thebacon-shor code,” Phys. Rev. Lett., vol. 98, p. 220502 (2007); C.Chamberland et al., “Overhead analysis of universal concatenated quantumcodes,” Phys. Rev. A, vol. 95, p. 022313 (2017).

In this disclosure, one of the focuses is evaluating the performance ofFTEC protocols (e.g., performing logical gates fault-tolerantly is notconsidered). The pseudo-threshold of an error correction protocol can bedefined to be the value of p such that{tilde over (p)}(p)=p ^((C)) _(L)(p).   (3)Note that it is desirable to have {tilde over (p)} on the left of Eq.(3) instead of p since one wants an encoded qubit to have a lowerlogical failure rate than an unencoded idle qubit. From the above noisemodel, a resting qubit will fail with probability {tilde over (p)}.

III. Flag Error Correction for Small Distance Codes

In this and the next section, a t-fault-tolerant flag error correctionprotocol is presented with distance-(2t+1) codes satisfying a certaincondition. This example approach extends to that introduced by Chao andReichardt (See R. Chao and B. W. Reichardt, “Quantum error correctionwith only two extra qubits,” arXiv:quant-ph/1705.02329 (2017)) fordistance three codes, which is first reviewed using the terminology inSection III A. In Section III B, the protocol for distance five CSScodes is presented, which is believed to be a useful and practical case,and which contains most of the main ideas of the general case (which isprovided in Section IV). In Section IV C some general remarks areprovided and in Section III C examples of how the protocol is applied tothe

19, 1, 5

color code are provided. Also shown is how the protocol can be appliedto the

17, 1, 5

color code. Further, comments are provided on the circuit requirementsfor measuring stabilizer generators of weight greater than six fordistance-5 codes.

A. Definitions and Flag 1-FTEC with Distance-3 Codes

FIG. 2 shows circuits for measuring the operator ZZZZ (can be convertedto any Pauli by single qubit Clifford's). Schematic block diagram 200(FIG. 2(a)) shows a non-fault-tolerant circuit. A single fault IZoccurring on the third CNOT (from the left) results in the bad errorIIZZ on the data block. Schematic block diagram 202 (FIG. 2(b)) shows aflag version of FIG. 2(a). An ancilla (flag) qubit prepared in |+

and two extra CNOT gates signals when a weight two data error is causedby a single fault. Subsequent error correction may identify which baderror occurred. Schematic block diagram 204 (FIG. 2(c)) shows analternative flag circuit with a different set of bad errors and lowerdepth than FIG. 2(b). All bad locations are illustrated in blue anddemarcated as such.

It is well known that with only a single measurement ancilla, a singlefault in a blue CNOT of the stabilizer measurement circuit shown in FIG.2 can result in a multi-weight error on the data block. This could causea distance-3 code to fail, or more generally could cause a distance-dcode to fail due to fewer than (d−1)/2 total faults. It can therefore besaid that the blue CNOTs are bad according to the following definition:

Definition 3. Bad Locations

A circuit location in which a single fault can result in a Pauli error Eon the data block with wt(E)≥2 will be referred to as a bad location.

As shown in FIG. 2(b), the circuit can be modified by including anadditional ancilla (flag) qubit, and two extra CNOT gates. Thismodification leaves the bad locations and the fault-free action of thecircuit unchanged. However, any single fault leading to an error E withwt(E)≥2 will also cause the measurement outcome of the flag qubit toflip. See D. P. DiVincenzo and P. Aliferis, “Effective fault-tolerantquantum computation with slow measurements,” Phys. Rev. Lett., vol. 98,p. 020501 (2007). The following definitions will be useful:

Definition 4. Flags and Measurements

Consider a circuit for measuring a stabilizer generator that includes atleast one flag ancilla. The ancilla used to infer the stabilizer outcomeis referred to as the measurement qubit. One can say the circuit hasflagged if the eigenvalue of a flag qubit is measured as −1. If theeigenvalue of a measurement qubit is measured as −1, one can say thatthe measurement qubit flipped.

Definition 5. t-Flag Circuit

A circuit C(P) for measuring a weight-w Pauli P is a t-flag circuit ifthe following is satisfied: For any set of υ faults at t or fewerlocations in C(P) resulting in an error E with min(wt(E), wt(EP))>υ, thecircuit C(P) flags.

Note that any faults occurring in a circuit measuring a stabilizer g ofweight-4 will result in an error E with min(wt(E), wt(Eg))≤2. Hence thecircuits shown in FIGS. 2(b) and 2(c) measuring a stabilizer Z^(⊗4) arein fact examples of t-flag circuits for any t. In Section IV B, ageneral construction for t-flag circuits which requires only one flagqubit is given.

It is also useful to define υ-bad errors.

Definition 6. υ-Bad Errors

For a given t-flag measurement circuit, one can say all data errorsresulting from up to υ≤t faults that lead to a flag are that circuit'sυ-bad errors.

Note that the set of υ-bad errors from a circuit can include theidentity, and weight one errors. When clear by the context, a bad errorwill be written in place of υ-bad error.

Suppose a 1-flag circuit's 1-bad errors all have distinct syndromes. Anyfault leading to an error of weight greater than one will lead to aflag. Moreover, when a flag has occurred due to at most one fault, acomplete set of fault-free stabilizer measurements will infer the baderror. In fact, one would only require distinct syndromes for bad errorsthat are logically inequivalent, as defined below.

Definition 7. Stabilizer Error Correction

Given a stabilizer group S=

g₁, . . . ,g_(m)

, one can define the syndrome s(E) to be a bit string, with i'th bitequal to zero (one) if g_(i) and E commute (anti-commute). Let min wt(s)be a minimal weight correction E where s(E)=s. One can say operators Eand E′ are logically equivalent, written as

(E)=

(E′), iff E′∝gE for g∈S.

Let E(g_(i)) be the set of all 1-bad errors resulting from a flag inC(g_(i)). One can define the correction set

$\begin{matrix}{{\overset{\sim}{E}\left( {g_{i},s} \right)} = \left\{ \begin{matrix}{{{E\mspace{14mu}{if}\mspace{14mu}{s(E)}} = {{s\mspace{14mu}{for}\mspace{14mu}{all}\mspace{14mu} E} \in {ɛ\left( g_{i} \right)}}},} \\{\min\mspace{14mu}{{wt}(s)}\mspace{14mu}{{otherwise}.}}\end{matrix} \right.} & (4)\end{matrix}$

With the above definitions, one can construct a fault-tolerant flagerror correction protocol for d=3 stabilizer codes satisfying a certaincondition.

Flag 1-FTEC Condition:

Consider a stabilizer code S=

g₁,g₂, . . . ,g_(r)

and 1-flag circuits {C(g₁),C(g₂), . . . ,C (g_(r))}. All elements in theset {tilde over (E)}(g_(i),s) are logically equivalent.

In other words, this condition requires that any two errors that arisewhen a circuit C(g_(i)) flags must be distinguishable or be logicallyequivalent. For the following protocol to satisfy Definition 2, one canassume there is at most 1 fault. If the Flag 1-FTEC condition issatisfied, the protocol is implemented as follows:

Flag 1-FTEC Protocol:

Repeat the syndrome measurement using flag circuits until one of thefollowing is satisfied:

-   -   1. If the syndrome s is repeated twice in a row and there were        no flags, apply the correction min wt(s).    -   2. If there were no flags and the syndromes s₁ and s₂ from two        consecutive rounds differ, repeat the syndrome measurement using        non-flag circuits yielding syndrome s. Apply the correction min        wt(s).    -   3. If a circuit C(g_(i)) flags, stop and repeat the syndrome        measurement using non-flag circuits yielding syndrome s. Apply a        correction from {tilde over (E)}(g_(i),s).

A tree diagram for the flag 1-FTEC Protocol is illustrated in FIG. 3. Inparticular, FIG. 3 is a schematic block diagram 300 showing a treediagram illustrating the possible paths of the Flag 1-FTEC Protocol.Numbers at the end of the edges indicate which step to implement in theFlag 1-FTEC Protocol. A dashed line is followed when any of the 1-flagcircuits C(g_(i)) flags. Solid squares indicate a syndrome measurementusing 1-flag circuits whereas rings indicate a decision based onsyndrome outcomes. Note that, in this embodiment, the syndromemeasurement is repeated at most three times.

Here, the proof is outlined (for a proof of the general case, seeSection VII). To show that Flag 1-FTEC Protocol satisfies the criteriaof Definition 2, one can assume there is at most one fault during theprotocol. If a single fault occurs in either the first or second roundleading to a flag, repeating the syndrome measurement will correctlydiagnose the bad error. If there are no flags and a fault occurs whichcauses the syndromes in the first two rounds to change, then thesyndrome during the third round will correctly diagnose the error. Therecould also be a fault during either the first or second round that goesundetected. But since there were no flags it cannot spread to an errorof weight-2. In this case, applying a minimum weight correction based onthe measured syndrome of the second round will guarantee that the outputcodeword differs from a valid codeword by an error of weight at mostone. Note that the above argument applies irrespective of any errors onthe input state, hence the second criteria of Definition 2 is satisfied.It is worth pointing out that up to three repetitions are used in orderto guarantee that the second criteria of Definition 2 is satisfied(unless the code has the property that all states are at most aweight-one error away from a valid codeword, as in R. Chao and B. W.Reichardt, “Quantum error correction with only two extra qubits,”arXiv:quant-ph/1705.02329 (2017)).

FIG. 4(a) is a schematic block diagram 400 showing a representation ofthe Steane code where each circle is a qubit, and there is an X- and aZ-type stabilizer generator for each face. Stabilizer circuits arespecified from that in FIG. 2(a) after rotating the lattice such thatthe relevant face is on the bottom left. For a given circuit, each ofthe four bad errors has a different syndrome (with satisfied stabilizersrepresented by a plus). Note that for g=Z_(q1)Z_(q2)Z_(q3)Z_(q4),E(g)={I, Z_(q3)Z_(q4), X_(q2)Z_(q3)Z_(q4), Z_(q1)X_(q2), Z_(q4),Z_(q3)Z_(q4), X_(q3)Z_(q3)Z_(q4)}. Since the Steane code is a CSS code,the X component of a possible bad error will be corrected independently.Thus, in schematic block diagram 402 of FIG. 4(b), only Z errorcontributions are shown.

The Steane code is an example which satisfies the Flag 1-FTEC conditionwith a simple choice of circuits. To verify this, the representation ofthe Steane code given in FIG. 4(a) is useful. There is an X- and aZ-type stabilizer generator supported on the four qubits of each of thethree faces. First let us specify all six stabilizer measurementcircuits. The circuit that measures Z_(q1)Z_(q2)Z_(q3)Z_(q4) isspecified by taking qubits q₁, q₂, q₃, and q₄ to be the four data qubitsin descending order in the 1-flag circuit in FIG. 2(a). The other twoZ-stabilizer measurement circuits are obtained by first rotating FIG.4(a) by 120° and 240° and then using FIG. 2(a). The X-stabilizer circuitfor each face is the same as the Z-stabilizer circuit for that face,replacing CNOT gates acting on data qubits by XNOT gates. The set of allbad errors of the circuit in FIG. 2(a), e.g., the data errors whichresult from a single fault leading to a flag, are {I, Z_(q1), Z_(q4),Z_(q3)Z_(q4)}. As can be seen from FIG. 4(b), each of these has adistinct syndrome, thus the measurement circuit forZ_(q1)Z_(q2)Z_(q3)Z_(q4) satisfies the flag 1-FTEC condition, as do theremaining five measurement circuits by symmetry.

B. Flag 2-FTEC with Distance-5 Codes

Before explicitly describing the conditions and protocol, some of thecomplications that arise for codes with d>3 are discussed.

FIG. 5 is a schematic block diagram 500 showing a tree diagram for theFlag 2-FTEC protocol. Numbers at the end of the edges indicate whichstep to implement in the Flag 2-FTEC Protocol. A dashed line is followedwhen any of the 2-flag circuits C(g_(i)) flags. Solid squares indicate asyndrome measurement using 2-flag circuits whereas rings indicate adecision based on syndrome outcomes. Edges with different colorsindicate the current value of n_(diff) in the protocol. Note that, inthis embodiment, the protocol is repeated at most 7 times.

For distance-5 codes, it is desirable to ensure that if two faults occurduring the error correction protocol, the output state will differ froma codeword by an error of at most weight-two. For instance, if twofaults occur in a circuit for measuring a stabilizer of weight greaterthan four, the resulting error E on the data should satisfy wt(E)≤2unless there is a flag. In other words, all stabilizer generators shouldbe measured using 2-flag circuits.

In another case, two faults could occur during the measurement ofdifferent stabilizer generators g_(i) and g_(j). If two bad locationsfail and are both flagged, and assuming there are no more faults, themeasured syndrome will correspond to the product of the two bad errors.Consequently, one should store a table containing products of bad errorsfor each pair of stabilizers g_(i) and g_(j). One then decodes based onthe pair of bad errors that resulted in the measured syndrome, providedlogically inequivalent errors have distinct syndromes.

Before stating the protocol, some definitions from Section III A can beextended.

Consider a stabilizer code S=

g₁,g₂, . . . ,g_(r)

and t-flag circuits C(g_(i)) for measuring the generator g_(i). Beforeproceeding, one can define a general t-fault correction set in Eq. (5).

Definition 8. Flag Error Set

Let E(g_(i) ₁ , . . . ,g_(i) _(k) ,m) be the set of all errors caused byprecisely m faults spread amongst the circuits C(g_(i) ₁ ),C(g_(i) ₂ ),. . . ,C(g_(i) _(k) ) which all flagged.

Note that there could be more than one fault in a single circuit C(g_(i)_(k) ). The correction set is then defined as

$\begin{matrix}{{{\overset{\sim}{E}}_{t}^{m}\left( {g_{i_{1}},\ldots\mspace{14mu},g_{i_{k}},s} \right)} = \left\{ \begin{matrix}{\left. E \middle| {s(E)} \right. = {s\mspace{14mu}{for}\mspace{14mu}{all}\mspace{14mu}{elements}}} \\{{E \in {{ɛ\left( {g_{i_{1}},\ldots\mspace{14mu},g_{i_{k}},m} \right)} \times ɛ_{t - m}}},} \\{\min\mspace{14mu}{{wt}(s)}\mspace{14mu}{{otherwise}.}}\end{matrix} \right.} & (5)\end{matrix}$

Flag 2-FTEC Condition:

Consider a stabilizer code S=

g₁,g₂, . . . ,g_(r)

and 2-flag circuits {C(g₁),C(g₂), . . . ,C(g_(r))}. All elements withineach set {tilde over (E)}² ₂(g_(i),g_(j),s) and {tilde over (E)}¹₂(g_(i),s)∪{tilde over (E)}² ₂(g_(i),s) and {tilde over (E)}¹ ₂(g_(i),s)are logically equivalent (but may not be logically equivalent betweensets).

In order to state the protocol, one can define an update rule given asequence of syndrome measurements using t-flag circuits for the countersn_(diff) and n_(same) as follows:

Flag 2-FTEC Protocol—Update Rules:

Given a sequence of consecutive syndrome measurement outcomes s_(k) ands_(k+1):

-   -   1. If n_(diff)=0 and s_(k)≠s_(k+1), increase n_(diff) by one.    -   2. If n_(diff) didn't increase in the previous round, and        s_(k)≠s_(k+1), increase n_(diff) by one. (n_(diff) tracks the        minimum number of faults that could have caused the observed        syndrome outcomes. For example, if the sequence s₁, s₂, s₁ was        measured, n_(diff) would increase by one since a single        measurement fault could give rise to the given sequence. However        for the sequence s₁, s₂, s₁, s₂, n_(diff) would increase by        two.)    -   3. If a flag occurred two rounds ago and s_(k)=s_(k+1), increase        n_(same) by one.

For the following protocol to satisfy Definition 2, one can assume thereare at most 2 faults. If the Flag 2-FTEC condition is satisfied, theprotocol is implemented as follows:

Flag 2-FTEC Protocol—Corrections:

Set n_(diff)=0 and n_(same)=0.

Repeat the syndrome measurement using flag circuits until one of thefollowing is satisfied:

-   -   1. If at any time a syndrome s is repeated 3 times in a row and        there were no flags, apply the correction min wt(s).    -   2. If n_(diff)=2 and there were no flags, repeat the syndrome        using non-flag circuits yielding syndrome s. Apply the        correction min wt(s).    -   3. If any two circuits C(g_(i)) and C(g_(j)) have flagged.        Repeat the syndrome measurement using non-flag circuits yielding        syndrome s. Apply a correction from the set {tilde over (E)}²        ₂(g_(i),g_(j),s).    -   4. If any circuit C(g_(i)) has flagged and n_(diff)=1. Repeat        the syndrome using non-flag circuits yielding syndrome s. Apply        a correction from the set {tilde over (E)}¹ ₂(g_(i),s).

TABLE I Z part of the flag error set of Definition 8 for flag circuitsused to measure the stabilizers g₁ = Z₁Z₂Z₃Z₄ and g₃ = Z₁Z₂Z₃Z₄Z₅Z₆(here, errors equivalent up to the stabilizer being measured areremoved). Weight-4 measurement Weight-6 measurement Single-faultTwo-faults Single-fault Two-faults I, Z₁, Z₄ I, Z₁, Z₂, Z₃ I, Z₁, Z₆ I,Z₁, Z₂, Z₃, Z₄ Z₃Z₄ Z₄, Z₁Z₂ Z₁Z₂, Z₅Z₆ Z₅, Z₆, Z₁Z₂, Z₁Z₃ Z₁Z₄, Z₂Z₄Z₄Z₅Z₆ Z₁Z₄, Z₁Z₅, Z₁Z₆ Z₂Z₃, Z₂Z₆, Z₃Z₄ Z₃Z₆, Z₄Z₅, Z₄Z₆ Z₅Z₆, Z₁Z₂Z₃Z₁Z₅Z₆, Z₂Z₅Z₆ Z₃Z₄Z₅, Z₃Z₄Z₆ Z₃Z₅Z₆, Z₄Z₅Z₆

-   -   5. If any circuit C(g_(i)) has flagged, n_(diff)=0 and        n_(same)=1. Use the measured syndrome s from the last round.        Apply a correction from the set {tilde over (E)}¹        ₂(g_(i),s)∪{tilde over (E)}² ₂(g_(i),s).

The general protocol for codes of arbitrary distance is given in SectionIV.

C. Examples of Flag 2-FTEC Applied to d=5 Codes

FIG. 6 shows a schematic block diagram 600 of a 19-qubit 2D color codein FIG. 6(a) and schematic block diagram 602 of a 17-qubit 2D color codein FIG. 6(b). The X and Z stabilizers of the code are symmetric, givenby the vertices of each plaquette. Both codes have distance-5.

FIG. 7 illustrates 2-flag circuits with minimal number of flag qubitsand CNOT's. All circuits have the minimum number of CNOT gates and noneare 3-flag circuits. FIG. 7(a) is a schematic block diagram 700 showinga circuit for measuring the Pauli Z^(⊗6) using 2 flag qubits. FIG. 7(b)is a schematic block diagram 702 of a circuit for measuring the thePauli Z²³⁷ ⁸.

In this section, examples are given of the flag 2-FTEC protocol appliedto the 2-dimensional

19, 1, 5

and

17, 1, 5

color codes, (see FIG. 6(a) and FIG. 6(b)). One can first find 2-flagcircuits for all generators (weight-4 and -6 for the 19-qubit code andweight-4 and -8 for the 17-qubit code). It will also be shown that theflag 2-FTEC condition is satisfied for both codes.

For a 2-flag circuit, two faults leading to an error of weight-3 (up tomultiplication by the stabilizer) must always result in a flag. As shownin Section IV B, a single flag qubit is required to obtain a 2-flagcircuit. However, using two flag qubits and performing an exhaustivesearch, one finds that only three CNOT gates for a weight-6 stabilizerand four CNOT gates for a weight-8 stabilizer with the |+

state as control and |0

state as target are required (see FIG. 7). Furthermore, these circuitsrequire fewer time steps.

In Section IV C, it will be shown that the family color codes with ahexagonal lattice satisfy a sufficient condition which guarantees thatthe flag 2-FTEC condition is satisfied. However, there are codes that donot satisfy the sufficient condition but which nonetheless satisfy the2-Flag FTEC condition. For the 19-qubit and 17-qubit color codes, it wasverified numerically that the flag 2-FTEC condition was satisfied. Inparticular, in the case where the 2-flag circuits C(g_(i)) and C(g_(j))flag, the resulting errors belonging to the set {tilde over (E)}²₂(g_(i),g_(j),s) must be logically equivalent (which was verified to betrue). If a single circuit C(g_(i)) flags, there could either have beentwo faults in the circuit or a single fault along with another errorthat did not cause a flag. If the same syndrome is measured twice in arow after a flag, then errors in the set {tilde over (E)}¹₂(g_(i),s)∪{tilde over (E)}² ₂(g_(i),s) must be logically equivalent(which has been verified). If there is a flag but two differentsyndromes are measured in a row, errors belonging to the set {tilde over(E)}¹ ₂(g_(i),s) must be logically equivalent (as was already checked).The sets {tilde over (E)}^(m) ₂ for the 19-qubit code can be obtainedusing the Pauli's shown in Table I.

Given that the flag 2-FTEC condition is satisfied, the flag 2-FTECprotocol can be implemented following the steps of Section III B and thetree diagram illustrated in FIG. 5.

IV. Flag Error Correction Protocol for Arbitrary Distance Codes

In this section, the general flag t-FTEC protocol in Section IV A isfirst provided. In Section IV B, circuit constructions are given whichsatisfy the requirements of Definition 5. Lastly, in Section IV C, asufficient condition for stabilizer codes is given that allows one toprove flag FTEC can be applied to a number of infinite code families.

For convenience, some helpful definitions are provided below.

Definition 5. t-Flag Circuit

A circuit C(P) for measuring a weight-w Pauli P is a t-flag circuit ifthe following is satisfied: For any set of υ faults at t or fewerlocations in C(P) resulting in an error E with min(wt(E), wt(EP))>υ, thecircuit C(P) flags.

Definition 6. υ-Bad Errors

For a given t-flag measurement circuit, one can say all data errorsresulting from up to υ≤t faults that lead to a flag are that circuit'sυ-bad errors.

Definition 8. Flag Error Set

Let E(g_(i) ₁ , . . . ,g_(i) _(k) ,m) be the set of all errors caused byprecisely m faults spread amongst the circuits C(g_(i) ₁ ),C(g_(i) ₂ ),. . . ,C(g_(i) _(k) ) which all flagged.

The following correction set is also provided as a reminder:

$\begin{matrix}{{{\overset{\sim}{E}}_{t}^{m}\left( {g_{i_{1}},\ldots\mspace{14mu},g_{i_{k}},s} \right)} = \left\{ \begin{matrix}{\left. E \middle| {s(E)} \right. = {s\mspace{14mu}{for}\mspace{14mu}{all}\mspace{14mu}{elements}}} \\{{E \in {{ɛ\left( {g_{i_{1}},\ldots\mspace{14mu},g_{i_{k}},m} \right)} \times ɛ_{t - m}}},} \\{\min\mspace{14mu}{{wt}(s)}\mspace{14mu}{{otherwise}.}}\end{matrix} \right.} & (6)\end{matrix}$

A. Conditions and Protocol

In what follows, a generalization of the fault-tolerant error correctionprotocol presented in Section III B to stabilizer codes of arbitrarydistance is provided.

Flag t-FTEC Condition:

Consider a stabilizer code S=

g₁,g₂, . . . ,g_(r)

and t-flag circuits {C(g₁),C(g₂), . . . ,C(g_(r))}. For all positiveintegers m and k such that 1≤m<t and m+k<t, all elements within each set{tilde over (E)}^(t) _(t)(g_(i) ₁ , . . . ,g_(i) _(t) ,s) and ∪^(t−m)_(j=0){tilde over (E)}^(t−j) _(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s) and∪^(t−m−k) _(j=0){tilde over (E)}^(t−j−k) _(t)(g_(i) ₁ , . . . ,g_(i)_(m) ,s) are logically equivalent (but may not be equivalent betweensets). (Note that the set ∪^(t−m−k) _(j=0){tilde over (E)}^(t−j−k)_(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s)⊂∪^(t−m) _(j=0){tilde over(E)}^(t−j) _(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s) as such, the logicalequivalence of elements in the latter implies the logical equivalence ofelements in the former. However, this redundancy is included in the flagt-FTEC condition since these two cases are distinguished due to how theyare treated in the flag t-FTEC protocol.)

The above conditions help ensure that if there are at most t=└(d−1)/2┘faults, the protocol described below will satisfy the fault-tolerantconditions of Definition 2.

In order to state the protocol, one can define an update rule given asequence of syndrome measurements using t-flag circuits for the countersn_(diff) and n_(same) as follows:

Flag t-FTEC Protocol—Update Rules:

Given a sequence of consecutive syndrome measurement outcomes s_(k) ands_(k+1):

-   -   1. If n_(diff)=0 and s_(k)≠s_(k+1), increase n_(diff) by one.    -   2. If n_(diff) didn't increase in the previous round, and        s_(k)≠s_(k+1), increase n_(diff) by one. (n_(diff) tracks the        minimum number of faults that could have caused the observed        syndrome outcomes. For example, if the sequence s₁, s₂, s₁ was        measured, n_(diff) would increase by one since a single        measurement fault could give rise to the given sequence. However        for the sequence s₁, s₂, s₁, s₂, n_(diff) would increase by        two.)    -   3. If a flag occurred two rounds ago and s_(k)=s_(k+1), increase        n_(same) by one.

Flag t-FTEC Protocol—Corrections:

Set n_(diff)=0 and n_(same)=0.

Repeat the syndrome measurement using flag circuits until one of thefollowing is satisfied:

-   -   1. The same syndrome s is repeated t+1 times in a row and there        are no flags, apply the correction min wt(s).    -   2. There were no flags and n_(diff)=t. Repeat the syndrome        measurement using non-flag circuits yielding the syndrome s.        Apply the correction min wt(s).    -   3. Some set of t circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(t) )}        have flagged. Repeat the syndrome measurement using non-flag        circuits yielding syndrome s. Apply a correction from the set        {tilde over (E)}^(t) _(t)(g_(i) ₁ , . . . ,g_(i) _(t) ,s).    -   4. Some set of m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )}        have flagged with 1≤m<t and n_(same)=t−m+1. Use the last        measured syndrome s and apply a correction from the set ∪^(t−m)        _(j=0){tilde over (E)}^(t−j) _(t)(g_(i) ₁ , . . . ,g_(i) _(m)        ,s).    -   5. Some set of m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )}        have flagged with 1≤m<t and n_(diff)=t−m. Repeat the syndrome        measurement using non-flag circuits yielding syndrome s. Apply a        correction from the set {tilde over (E)}^(m) _(t)(g_(i) ₁ , . .        . g_(i) _(m) ,s).    -   6. Some set of in circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )}        have flagged with 1≤m<t, n_(diff)=k; m+k<t and n_(same)=t−m−k+1.        Use the syndrome s obtained during the last round and apply a        correction from the set ∪^(t−m−k) _(j=0){tilde over (E)}^(t−j−k)        _(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s).

From condition 1, the syndrome measurement is desirably repeated aminimum of t+1 times. In the worst case, t identical syndromes areobtained before a fault causes the t+1'th syndrome to change. This canoccur at most t times (with n_(diff)=t) in which case one repeats thesyndrome measurement using non-flag circuits. Thus the maximum number ofsyndrome measurement repetitions is t²+t+1 where the first t²+trepetitions are done using flag circuits and the last round is doneusing non-flag circuits.

For codes that satisfy the flag t-FTEC condition, it is shown in SectionVIII how to fault-tolerantly prepare and measure logical states usingthe flag t-FTEC protocol.

B. Circuits

In Section IV C it is shown that the family of surface codes, colorcodes with a hexagonal lattice and quantum Reed-Muller codes satisfied asufficient condition allowing them to be used in the flag t-FTECprotocol. The general 1-flag circuit construction of FIGS. 8(a)-8(c) andthe general 3-flag circuit construction of FIGS. 9(a)-9(b), can be usedas t-flag circuits for all of the codes in Section IV C (note that thecircuit in FIG. 2(b) is a 4-flag circuit which is used for measuringZ^(⊗4)).

1- and 2-Flag Circuits for Weight w Stabilizer Measurement:

1- and 2-flag circuit constructions are provided for measuring aweight-w stabilizer. The 1-flag circuit requires one flag qubit, and the2-flag circuit requires at most four flag qubits.

As was shown in R. Chao and B. W. Reichardt, “Quantum error correctionwith only two extra qubits,” arXiv:quant-ph/1705.02329 (2017), schematicblock diagram 800 of FIG. 8(a) illustrates a general 1-flag circuitconstruction for measuring the stabilizer Z^(⊗w) which requires only twoCNOT_(fm) gates. Without loss of generality in proving that these are 1-and 2-flag circuits, one can assume that all faults occurred on CNOTgates. This is because any set of υ faults (including those at idle,preparation or measurement locations) will have the same output Paulioperator and flag measurement results as some set of at most υ faults onCNOT gates (since every qubit is involved in at least one CNOT).

To see that the first construction is a 1-flag circuit, note a IZ erroroccurring on any CNOT will give rise to a flag unless it occurs on thefirst or last CNOT_(dm) gates or the last CNOT_(fm) gate. However, sucha fault on any of these three gates can give rise to an error of weightat most one (after multiplying by the stabilizer Z^(⊗w)). One can alsoverify that if there are no faults, the circuit in FIG. 8(a) implementsa projective measurement of Z^(⊗w) without flagging. One can check thatthe circuit preserves the stabilizer group generated by Z^(⊗w) and X oneach ancilla prepared in the |+

state and Z on each ancilla prepared in the |0

state. By using pairs of CNOT_(fm) gates, this construction satisfiesthe requirement.

In this section, a general 2-flag circuit construction is given (seeschematic block diagram 802 of FIG. 8(b) for an example). The circuitconsists of pairs of CNOT_(fm) gates each connected to a different flagqubit prepared in the |+

state and measured in the X basis. The general 2-flag circuitconstruction involves the following placement of w/2−1 pairs ofCNOT_(fm) gates:

-   -   1. Place a CNOT_(fm) pair between the first and second last        CNOT_(dm) gates.    -   2. Place a CNOT_(fm) pair between the second and last CNOT_(dm)        gates.    -   3. After the second CNOT_(fm) gate, place the first CNOT_(fm)        gate of the remaining pairs after every two CNOT_(dm) gates. The        second CNOT_(fm) gate of a pair is placed after every three        CNOT_(dm) gates.        As shown in schematic block diagram 804 in FIG. 8(c), it is        possible to reuse some flag qubits to measure multiple pairs of        CNOT_(fm) gates at the cost of introducing extra time steps into        the circuit. For this reason, at most four flag qubits will be        needed, however, if w≤8, then w/2−1 flag qubits are sufficient.

It can now be shown that the above construction satisfies therequirements of a 2-flag circuit. If one CNOT gate fails, by an argumentanalogous to that used for the 1-flag circuit, there will be a flag oran error of at most weight-one on the data. If the first pair ofCNOT_(fm) gates fail causing no flag qubits to flag, after multiplyingthe data qubits by Z^(⊗w) the resulting error E_(r) will havewt(E_(r))≤2. For any other pair of CNOT_(fm) gates that fail causing anerror of weight greater than two on the data, by construction there willalways be another CNOT_(fm) gate between the two that fail which willpropagate a Z error to a flag qubit causing it to flag. Similarly, ifpairs of CNOT_(dm) gates fail resulting in the error E_(r) will havewt(E_(r))≤2 on the data, by construction there will always be an oddnumber of Z errors propagating to a flag qubit due to the CNOT_(fm)gates in between the CNOT_(dm) gates that failed causing a flag qubit toflag. The same argument applies if a failure occurs between a CNOT_(dm)and CNOT_(fm) gate.

Use of Flag Information:

As seen in FIGS. 8(a), 8(c), 9(a) and 9(b), flag circuits can use morethan one flag qubit. The extra flag qubits could be used to reduce thesize of the correction sets (define in Eq. (5)) when verifying the Flagt-FTEC condition of see Section IV. To do so, one can first define f,where f is a bit string of length u where u is the number of flag qubitswith f_(i)=1 if the i'th flag qubit flagged and 0 otherwise. In thiscase the correction set is defined as

$\begin{matrix}{{{\overset{\sim}{E}}_{t}^{m}\left( {g_{i_{1}},\ldots\mspace{14mu},g_{i_{m}},s,f_{i_{1}},\ldots\mspace{14mu},f_{i_{m}}} \right)} = \left\{ \begin{matrix}\begin{Bmatrix}{E \in {{ɛ\left( {g_{i_{1}},\ldots\mspace{14mu},g_{i_{k}},m,,f_{i_{1}},\ldots\mspace{14mu},f_{i_{m}}} \right)} \times ɛ_{t - m}}} \\{{{such}\mspace{14mu}{that}\mspace{14mu}{s(E)}} = s}\end{Bmatrix} \\{{\left\{ {E_{\min}(s)} \right\}\mspace{14mu}{otherwise}},}\end{matrix} \right.} & (7)\end{matrix}$where E(g_(i) ₁ , . . . ,g_(i) _(k) ,m,,f_(i) ₁ , . . . ,f_(i) _(m) ) isthe set of all errors caused by precisely m faults spread amongst thecircuits C(g_(i) ₁ ),C(g_(i) ₂ ), . . . ,C(g_(i) _(k) ) which each hadthe flag outcome f_(i) ₁ , . . . ,f_(i) _(m) .

Hence only errors which result from the measured flag outcome would bestored in the correction set. This could potentially broaden the familyof codes which satisfy the Flag t-FTEC condition.

C. Sufficient Condition and Satisfying Code Families

The general flag t-FTEC condition can be difficult to verify for a givencode since it depends on precisely which t-flag circuits are used. Asufficient (but not necessary) condition that implies the flag t-FTECcondition is as follows:

Sufficient Flag t-FTEC Condition:

Given a stabilizer code with with distance d>1, and S=

g₁,g₂, . . . ,g_(r)

, one requires that for all υ=0,1, . . . t, all choices Q_(t−υ)of 2(t−υ)qubits, and all subsets of υ stabilizer generators {g_(i) ₁ , . . .,g_(i) _(υ) }∪{g₁, . . . ,g_(r)}, there is no logical operator l∈N(S)\Ssuch thatsupp(l)⊂supp(g _(i) ₁ )∪. . . ∪supp(g _(i) _(υ) )∪Q _(t−υ),   (8)where N(S) is the normalizer of the stabilizer group.

If this condition holds, then the t-FTEC condition is implied for anychoice of t-flag circuits {C(g₁),C(g₂), . . . ,C(g_(r))}. To prove this,one must show that particular sets do not contain elements that differby a logical operator. First consider {tilde over (E)}^(t) _(t)(g_(i) ₁, . . . ,g_(i) _(t) ,s), which has all elements supported withinsupp(g_(i) ₁ )∪. . . ∪supp(g_(i) _(t) ). The sufficient conditionimplies this region cannot contain a logical operator, and therefore theproduct of two Paulis supported in this region cannot be a logicaloperator. Now consider the set ∪^(t−m) _(j=0){tilde over (E)}^(t−j)_(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s) for a particular 1≤m<t. An error Efrom this set will have support in the union of the support of the mstabilizer generators {g_(i) ₁ , . . . ,g_(i) _(m) }, along with up tot−m other single qubits. Another error E′ from this set will havesupport in the union of support of the same m stabilizer generators{g_(i) ₁ , . . . ,g_(i) _(m) }, along with up to t−m other potentiallydifferent single qubits. If the sufficient condition holds, thensupp(EE′) cannot contain a logical operator. The other cases followsimilarly.

The sufficient flag t-FTEC condition is straightforward to verify for anumber of code families with a lot of structure in their stabilizergenerators and logical operators. Here, several representative examplesare provided.

Surface Codes t-Flag FTEC:

The rotated surface code family

d²−1, 1, d

for all odd d=2t+1 (see FIG. 10) satisfies the flag t-FTEC conditionusing any 1-flag circuits. See S. Bravyi and A. Kitaev, “Quantum codeson a lattice with boundary,” arXiv:quant-ph/9811052 (1998); E. Dennis etal., “Topological quantum memory,” Journal of Mathematical Physics, vol.43, pp. 4452-4505 (2002).

Firstly, since the generators are all weight-4, any 1-flag circuit is at-flag circuit.

As a CSS code, one can restrict attention to purely X-type and Z-typelogical operators. An X type logical operator must have at least onequbit in each of the 2t+1 rows of the lattice shown. However, eachstabilizer only contains qubits in two different rows. Therefore, with υstabilizer generators, at most 2υ of the rows could have support. Withan additional 2(t−υ) qubits, at most 2t rows can be covered, which isfewer than the number of rows, and therefore no logical X operator issupported on the union of the support of υ stabilizers and 2(t−υ)qubits. An analogous arguments holds for Z-type logical operators,therefore the sufficient t-FTEC condition is satisfied.

FIG. 10 is a schematic block diagram 1000 illustrating an example d=5rotated surface code. Qubits are represented by white circles, and X andZ stabilizer generators are represented by red and green faces. As inthe example, any logical X operator has X operators acting on at leastfive qubits, with at least one in each row of the lattice, involving aneven number in any green face. In this case, no two stabilizergenerators can have qubits in five rows, and therefore cannot contain anX type logical operator. The argument is analogous for logical Zoperators.

Color Codes t-flag FTEC:

Here, it is shown that any distance d=(2t+1) self-dual CSS code with atmost weight-6 stabilizer generators satisfies the flag t-FTEC conditionusing any 2-flag circuits. Examples include the hexagonal color codefamily

(3d²+1)/4, 1, d

(see FIG. 6(a)). See H. Bombin et al., “Topological quantumdistillation,” Phys. Rev. Lett., vol. 97, p. 180501 (October 2006).

Firstly, since the generators are at most weight-6, any 2-flag circuitis a t-flag circuit.

As a self-dual CSS code, X and Z type stabilizer generators areidentically supported and one can consider a pure X-type logicaloperator without loss of generality.

Consider an X type logical operator l such thatsupp(l)⊂supp(g _(i) ₁ )∪. . . ∪supp(g _(i) _(υ) )∪Q _(t−υ),   (9)for some set of υ stabilizer generators {g_(i) ₁ , . . . ,g_(i) _(υ)}⊂{g₁, . . . ,g_(r)} along with 2(t−υ) other qubits Q_(t−υ). Restrictedto the support of any of the υ stabilizers g_(i), l|_(gi) must haveweight 0, 2, 4, or 6 (otherwise it would anti-commute with thecorresponding Z type stabilizer). If the restricted weight is 4 or 6,one can produce an equivalent lower weight logical operator l′=g_(i)l,which still satisfies Eq. (9). Repeating this procedure until the weightof the logical operator can no longer be reduced yields a logicaloperator l_(min) which has weight either 0 or 2 when restricted to thesupport of any of the υ stabilizer generators. The total weight ofl_(min) is then at most 2υ+2(t−υ)=2t, which is less than the distance ofthe code, giving a contradiction which therefore implies that l couldnot have been a logical operator. An analogous arguments holds forZ-type logical operators, therefore the sufficient t-FTEC condition issatisfied.

This proof can be easily extended to show that any distance d=(2t+1)self-dual CSS code with at most weight-2υ stabilizer generators for someinteger υ satisfies the flag t′-FTEC condition using any (υ−1)-flagcircuits, where t′=t/└υ/2┘.

Quantum Reed-Muller Codes 1-flag FTEC:

The

n=2^(m)−1, k=1, d=3

quantum Reed-Muller code family for every integer m≥3 satisfies the flag1-FTEC condition using any 1-flag circuits for the standard choice ofgenerators.

One can use the following facts about the Quantum Reed-Muller codefamily (see Section IX and J. T. Anderson et al., “Fault-tolerantconversion between the steane and reed-muller quantum codes,” Phys. Rev.Lett., vol. 113, p. 080501 (2014). for proofs of these facts): (1) Thecode is CSS, allowing us to restrict to pure X type and pure Z typelogical operators, (2) all pure X or Z type logical operators have oddsupport, (3) every X-type stabilizer generator has the same support assome Z-type stabilizer generator, and (4) every Z-type stabilizergenerator is contained within the support of an X type generator.

One only needs to prove the sufficient condition for υ=0, 1 in thiscase. For υ=0, no two qubits can support a logical operator, as anylogical operator has weight at least three. For υ=1, assume the supportof an X-type stabilizer generator contains a logical operator l. Thatlogical operator l cannot be Z type or it would anti-commute with theX-stabilizer due to its odd support. However, by fact (3), there is a Ztype stabilizer with the same support as the X type stabilizer,therefore implying l cannot be X type either. Therefore, bycontradiction one can conclude that no logical operator can be containedin the support of an X stabilizer generator. Since every otherstabilizer generator is contained within the support of an X-typestabilizer generators, a logical operator cannot be contained in thesupport of any stabilizer generator.

Note that the Hamming code family has a stabilizer group which is aproper subgroup of that of the quantum Reed-Muller codes described here.The X-type generators of each Hamming code are the same as for a quantumReed-Muller code, and the Hamming codes are self-dual CSS codes. It isclear that the sufficient condition cannot be applied to the Hammingcode since it has even-weight Z-type logical operators (which arestabilizers for the quantum Reed-Muller code) supported within thesupport of some stabilizer generators.

Codes which Satisfy Flag t-FTEC Condition but not Sufficient Conditions:

Note that there are codes which satisfy the general flag t-FTECcondition but not the sufficient condition presented in this section. Anexample of such a code is the

5, 1, 3

code (see Table VII for the codes stabilizer generators and logicaloperators). Another example includes the Hamming codes as was explainedin the discussion on quantum Reed-Muller codes.

V. Circuit Level Noise Analysis

The purpose of this section is to demonstrate explicitly the flag 2-FTECprotocol, and to identify parameter regimes in which flag FTEC presentedboth here and in other works offers advantages over other existing FTECschemes. In

TABLE II Table containing pseudo-threshold values for the example errorcorrection protocol applied to the

 19, 1, 5 

 color code for p = p, p = p/10 and p = p/100. three-qubit, flag ECpseudo-threshold

 19, 1, 5 

 with {tilde over (p)} = p p_(pseudo) = (1.14 ± 0.02) × 10⁻⁵

 19, 1, 5 

 with {tilde over (p)} = p/10 p_(pseudo) = (6.70 ± 0.07) × 10⁻⁵

 19, 1, 5 

 with {tilde over (p)} = p/100 p_(pseudo) = (7.74 ± 0.16) × 10⁻⁵Section V A the logical failure rates of the

19, 1, 5

color code was analyzed and its pseudo-threshold for the three choicesof {tilde over (p)} computed. In Section V B, logical failure rates ofseveral fault-tolerant error correction schemes applied todistance-three and distance-five stabilizer codes were compared . Thestabilizers for all of the studied codes are given in Table VII. Logicalfailure rates are computed using the full circuit level noise model andsimulation methods described in Section II B.

A. Numerical Analysis of the 19, 1, 5 Color Code

The full circuit-level noise analysis of the disclosed fault-tolerantprotocol applied to the

19, 1, 5

color code was performed using the stabilizer measurement circuits ofFIG. 2(b) and FIG. 7(a).

In the weight-six stabilizer measurement circuit of FIG. 7(a), there are9 CNOT gates, two measurement and state-preparation locations, and 218resting qubit locations. When measuring all stabilizer generators usingnon-flag circuits, there are 42 CNOT and 42 XNOT gates, 18 measurementand state-preparation locations, and 2196 resting qubit locations.Consequently, one expects the error suppression capabilities of the flagEC scheme to depend strongly on the number of idle qubit locations.

FIG. 11 is a graph 1100 showing the logical failure rates of the

19, 1, 5

color code after performing a round of flag EC presented in Section IIIB for the three noise models described in Section II B. The dashedcurves represent the lines {tilde over (p)}=p, {tilde over (p)}=p/10 and{tilde over (p)}=p/100. The crossing point between {tilde over (p)} andthe curve corresponding to

({tilde over (p)}) in Eq. (3) gives the pseudo-threshold.

Pseudo-thresholds of the

19, 1, 5

code were obtained using the methods of Section II B. Recall that forextending the lifetime of a qubit, which when idle fails withprobability {tilde over (p)}, the probability of failure afterimplementing a FTEC protocol should be smaller than {tilde over (p)}.The pseudo-threshold using Eq. (3) for the three cases where idle qubitsfailed with probability {tilde over (p)}=p, {tilde over (p)}=p/10 and{tilde over (p)}=p/100 were calculated. The results are shown in TableII.

The logical failure rates for the three noise models are shown in FIG.11. It can be seen that when the probability of error on a resting qubitdecreases from p to p/10, the pseudo-threshold improves by nearly afactor of six showing the strong dependence of the scheme on theprobability of failure of idle qubits.

B. Comparison of Flag Fault-Tolerant Error Correction Schemes

FIG. 12 is a diagram 1200 showing graphs 12(a)-(f) for the logicalfailure rates for various error correction methods, including variousfault-tolerant error correction methods applied to the

5, 1, 3

code,

7, 1, 3

Steane code and the

19, 1, 5

color code. The dashed curves correspond to the lines {tilde over(p)}=p, {tilde over (p)}=p/10 and {tilde over (p)}=p/100. In FIGS.12(a), (c) and (e), the flag error correction methods are applied to the

5, 1, 3

and Steane code and the results are compared with the d=3 surface codeand Steane error correction applied to the Steane code. In FIGS. 12(b),(d) and (f), the example flag error correction methods are applied tothe

19, 1, 5

color code, and the results are compared with the d=5 surface code andSteane error correction applied to the

19, 1, 5

color code.

These numerical results suggest the following fault-tolerant experimentsof the schemes considered herein for extending the fidelity of a qubit.(1) If 7≤n≤16, only the 5 and 7 qubit codes with flag 1-FTEC areaccessible. However, performance is much worse than higher qubitalternatives unless {tilde over (p)}/p is small. (2) For 17≤n≤34, thed=3 surface code seems the most promising, unless {tilde over (p)}/p isvery small, in which case flag 2-FTEC with the 19-qubit code could bebetter. (3) For 35≤n≤48, Steane EC with d=3 code is better than allother approaches studied, except for very low p where flag 2-FTEC shouldbe better due to ability to correct two rather than just one fault. (4)For n≥49, the d=5 surface code is expected to perform better than theother alternatives below pseudo-threshold.

The most promising schemes for testing fault-tolerance in near termquantum devices are those which achieve high pseudo-thresholds whilemaintaining a low qubit overhead. The flag-FTEC protocol presented inthis disclosure uses fewer qubits compared to other well knownfault-tolerance schemes but typically has increased circuit depth. Inthis section, the flag-FTEC protocol of Sections III A and III B isapplied to the

5, 1, 3

,

7, 1, 3

and

19, 1, 5

codes. Here, logical failure rates for three values of {tilde over (p)}are compared with Steane error correction applied to the

7, 1, 3

and

19, 1, 5

codes and d=3 and d=5 surface codes. More details on surface codes andSteane error correction are provided in Sections X and XI.

Results of the logical failure rates for {tilde over (p)}=p, {tilde over(p)}=p/10 and {tilde over (p)}=p/100 are shown in FIG. 12. Variouspseudo-thresholds and required time-steps for the consideredfault-tolerant error correction methods are given in Tables III and IV.

The circuits for measuring the stabilizers of the 5-qubit code weresimilar to the ones used in FIG. 2(b) (for an X Pauli replace the CNOTby an XNOT). For flag-FTEC methods, it can be seen that the

5, 1, 3

code always achieves lower logical failure rates compared to the

7, 1, 3

code. However, when {tilde over (p)}=p, both the d=3 surface code aswell as Steane-EC achieves lower logical failure rates (with Steane-ECachieving the best performance). For {tilde over (p)}=p/10, flag-ECapplied to the

5, 1, 3

code achieves nearly identical logical failure rates compared to the d=3surface code. For {tilde over (p)}=p/100, flag-EC applied to the

5, 1, 3

code achieves lower logical failure rates than the d=3 surface code butstill has higher logical failure rates compared to Steane-EC.

One can also note that the pseudo-threshold increases when {tilde over(p)} goes from p to p/10 for both the

5, 1, 3

and

7, 1, 3

codes under flag-EC. This is primarily due to the large circuit depth inflag-EC protocols since idle qubits locations

TABLE III Distance-three pseudo-threshold results for variousfault-tolerant error correction protocols and noise models applied tothe 

 5, 1, 3 

 , 

 7, 1, 3 

 and d = 3 surface code. Also included are the number of time stepsrequired to implement the protocols. Fault-tolerant error correctionscheme Noise model Number of qubits Time steps (T_(time))Pseudo-threshold Flag-EC 

 5, 1, 3 

{tilde over (p)} = p 7 64 ≤ T_(time) ≤ 88  p_(pseudo) = (7.09 ± 0.03) ×10⁻⁵ Flag-EC 

 7, 1, 3 

9 72 ≤ T_(time) ≤ 108 p_(pseudo) = (3.39 ± 0.10) × 10⁻⁵ d = 3 Surfacecode 17 ≥18 p_(pseudo) = (3.29 ± 0.16) × 10⁻⁴ Steane-EC 

 7, 1, 3 

≥35 15 p_(pseudo) = (6.29 ± 0.13) × 10⁻⁴ Flag-EC 

 5, 1, 3 

{tilde over (p)} = p/10 7 64 ≤ T_(time) ≤ 88  p_(pseudo) = (1.11 ± 0.02)× 10⁻⁴ Flag-EC 

 7, 1, 3 

9 72 ≤ T_(time) ≤ 108 p_(pseudo) = (8.68 ± 0.15) × 10⁻⁵ d = 3 Surfacecode 17 ≥18 p_(pseudo) = (1.04 ± 0.02) × 10⁻⁴ Steane-EC 

 7, 1, 3 

≥35 15 p_(pseudo) = (3.08 ± 0.01) × 10⁻⁴ Flag-EC 

 5, 1, 3 

{tilde over (p)} = p/100 7 64 ≤ T_(time) ≤ 88  p_(pseudo) = (2.32 ±0.03) × 10⁻⁵ Flag-EC 

 7, 1, 3 

9 72 ≤ T_(time) ≤ 108 p_(pseudo) = (1.41 ± 0.05) × 10⁻⁵ d = 3 Surfacecode 17 ≥18 p_(pseudo) = (1.37 ± 0.03) × 10⁻⁵ Steane-EC 

 7, 1, 3 

≥35 15 p_(pseudo) = (3.84 ± 0.01) × 10⁻⁵significantly outnumber other gate locations. For the surface code, theopposite behaviour is observed. As was shown in A. G. Fowler et al.,“Surface codes: Towards practical large-scale quantum computation,”Phys. Rev. A, vol. 86, p. 032324 (2012), CNOT gate failures have thelargest impact on the pseudo-threshold of the surface code. Thus, whenidle qubits have lower failure probability, lower physical error rateswill be required in order to achieve better logical failure rates. Forinstance, if idle qubits never failed, then performing error correctionwould be guaranteed to increase the probability of failure due to thenon-zero failure probability of other types of locations (CNOT,measurements and state-preparation). Lastly, the pseudo-threshold forSteane-EC also decreases with lower idle qubit failure rates, but thechange in pseudo-threshold is not as large as the surface code. This isprimarily due to the fact that all CNOT gates are applied transversallyin Steane-EC, so that the pseudo-threshold is not as sensitive to CNOTerrors compared to the surface code. Furthermore, most high-weighterrors arising during the state-preparation of the logical ancilla'swill be detected (see Section X). Hence, idle qubit errors play a largerrole than in the surface code, but Steane-EC has fewer idle qubitlocations compared to flag-EC (see Table III for the circuit depths ofall schemes).

Although Steane-EC achieves the lowest logical failure rates compared tothe other fault-tolerant error correction schemes, it requires a minimumof 35 qubits (more details are provided in Section X). In contrast, thed=3 surface code requires 17 qubits, and flag-FTEC applied to the

5, 1, 3

code requires only 7 qubits. Therefore, if the probability of idle qubiterrors is much lower than gate, state preparation and measurementerrors, flag-FTEC methods could be good candidates for earlyfault-tolerant experiments.

It is important to keep in mind that for flag EC methods ofdistance-three codes considered in this section, the same ancilla qubitsare used to measure all stabilizers. A more parallelized version offlag-FTEC applied to the

7, 1, 3

code using four ancilla qubits instead of two is considered in SectionXII.

TABLE IV Distance-five pseudo-threshold results for variousfault-tolerant error correction protocols and noise models applied tothe 

 19, 1, 5 

 color code and d = 5 surface code. Also included is the number of timesteps required to implement the protocols. Fault-tolerant errorcorrection scheme Noise model Number of qubits Time steps (T_(time))Pseudo-threshold Flag-EC 

 19, 1, 5 

  {tilde over (p)} = p 22 486 ≤ T_(time) ≤ 1092 p_(pseudo) = (1.14 ±0.02) × 10⁻⁵ d = 5 Surface code 49 ≥18 p_(pseudo) = (9.41 ± 0.17) × 10⁻⁴Steane-EC 

 19, 1, 5 

  ≥95 15 p_(pseudo) = (1.18 ± 0.02) × 10⁻³ Flag-EC 

 19, 1, 5 

  {tilde over (p)} = p/10 22 486 ≤ T_(time) ≤ 1092 p_(pseudo) = (6.70 ±0.07) × 10⁻⁵ d = 5 Surface code 49 ≥18 p_(pseudo) = (7.38 ± 0.22) × 10⁻⁴Steane-EC 

 19, 1, 5 

  ≥95 15 p_(pseudo) = (4.42 ± 0.27) × 10⁻⁴ Flag-EC 

 19, 1, 5 

  {tilde over (p)} = p/100 22 486 ≤ T_(time) ≤ 1092 p_(pseudo) = (7.74 ±0.16) × 10⁻⁵ d = 5 Surface code 49 ≥18 p_(pseudo) = (2.63 ± 0.18) × 10⁻⁴Steane-EC 

 19, 1, 5 

  ≥95 15 p_(pseudo) = (5.60 ± 0.43) × 10⁻⁵

In computing the number of time steps for t-flag fault-tolerant errorcorrection protocols, a lower bound is given in the case where there areno flags and the same syndrome is repeated t+1 times. In Section IV itis shown that the full syndrome measurement for flag-FTEC is repeated atmost t²+t+1 times where t=└(d−1)/2┘. An upper bound is thus obtainedfrom a worst case scenario where syndrome measurements are repeatedt²+t+1 times.

For distance-five codes, the first thing to notice from FIG. 12 is thatthe slopes of the logical failure rate curves of flag-EC applied to the

19, 1, 5

code and d=5 surface code are different from the slopes of Steane-ECapplied to the

19, 1, 5

code. In particular, p_(L)=cp³+

(p⁴) for flag-EC and the surface code whereas p_(L)=c₁p²+c₂p³+

(p⁴) for Steane-EC (c, c₁ and c₂ are constants that depend on the codeand FTEC method). The reason that Steane-EC has non-zero

(p²) contributions to the logical failure rates is that there areinstances where errors occurring at two different locations can lead toa logical fault. Consequently, the Steane-EC method that was used is notstrictly fault-tolerant according to Definition 2. In Section X, moredetails on the fault tolerant properties of Steane-EC are provided.

For d=5, the surface code achieves significantly lower logical failurerates compared to all other distance 5 schemes but uses 49 qubitsinstead of 22 for the

19, 1, 5

code. Furthermore, notice the differences in the slopes of flag-2 FTECwith Steane-EC applied to the

19, 1, 5

code which results in a regime where flag-2 FTEC achieves lower logicalfailure rates compared to Steane-EC. For {tilde over (p)}=p/100, it canbe seen in FIG. 12 that this regime occurs when p{tilde under (≲)}10⁻⁴.One can also note that the pseudo-threshold of flag-EC applied to the

19, 1, 5

color code increases for all noise models whereas the pseudo-thresholddecreases for the other FTEC schemes. Again, this is due to the factthat flag-EC has a larger circuit depth compared to the other FTECmethods and is thus more sensitive to idle qubit errors.

Comparing the

19, 1, 5

color code to all the d=3 schemes, if {tilde over (p)}=p/100, the19-qubit color code acheives lower logical failure rates than both thesurface code and Steane-EC applied to the

7, 1, 3

code. Thus if idle qubit locations have low probability of failure,using flag error correction with only 22 qubits outperforms Steane errorcorrection (which uses a minimum of 35) and the d=3 surface code whichuses 17 qubits.

Note the considerable number of time steps involved in a round of flagerror correction, particularly in the d=5 case in Table IV. For manyapplications, this is a major drawback, for example for quantumcomputation when the time of an error correction round dictates the timeof a logical gate. However there are some cases in which having a largernumber of time-steps in an EC round while holding the logical error ratefixed is advantageous as it corresponds to a longer physical lifetime ofthe encoded information. Such schemes could be useful for example indemonstrating that encoded logical quantum information can be stored forlonger time scales in the lab using repeated rounds of fault-toleranterror correction.

VI. Review

Building on definitions and a new flag fault-tolerant error correctionprotocol applied to distance-three and -five codes presented in SectionIII, in Section IV A a general FTEC protocol was presented, which wascalled flag t-FTEC, and which is applicable to stabilizer codes ofdistance d=2t+1 that satisfy the flag t-FTEC condition. The protocolmakes use of flag ancilla qubits which signal when υ faults lead toerrors of weight greater than υ. In Sections III C and IV B explicitcircuit constructions were given, including those needed for distance 3and 5 codes measuring stabilizers of weight 4, 6 and 8. In Section IV C,a sufficient condition for codes to satisfy the requirements for flagt-FTEC was given. Quantum Reed-Muller codes, Surface codes and hexagonallattice color codes were shown to be families of codes that satisfy thesufficient condition.

The flag t-FTEC protocol could be useful for fault-tolerant experimentsperformed in near term quantum devices since it tends to use fewerqubits than other FTEC schemes such as Steane, Knill and Shor EC. InSection V B, numerical evidence was given that with only 22 qubits, theflag 2-FTEC protocol applied to the

19, 1, 5

color code can achieve lower logical failure rates than other codesusing similar numbers of qubits such as the rotated distance-3 surfacecode and Steane-EC applied to the Steane code.

VII. Proof that the Flag t-FTEC Protocol Satisfies the Fault-TolerantCriteria of Definition (2)

Consider the flag t-FTEC protocol described in Section IV.

Claim 1. If the flag t-FTEC condition is satisfied, then both criteriaof Definition 2 will be satisfied.

Proof. One can assume that there are at most t-faults during the flagt-FTEC protocol. Also, one can define a benign fault to be a fault thateither leaves the syndrome measurement unchanged or that occurs at atime-step of a stabilizer measurement circuit such that it goesundetected.

By repeating the syndrome measurement using flag circuits, the followingcases exhaust all possibilities for the occurrence of at most t faults.

Case 1: The same syndrome is measured t+1 times in a row and there areno flags.

Since there can be at most t-faults, at least one round (say r) had tohave been fault-free. Thus the errors on the data block during round rwere correctly diagnosed. Applying min wt(s) will remove those errors.Furthermore, since all syndrome measurements are identical and there areno flags, there can be at most t errors which are introduced on the datablocks from faults during syndrome measurement rounds (excluding roundr). Since none of the errors change the syndrome, after applying thecorrection, the output state can differ from a codeword by an error ofweight at most t. Thus both conditions of Definition 2 are satisfied.

Case 2: There are no flags and n_(diff)=t.

By definition, the only way that n_(diff)=t is if there were t-faultsthat changed the syndrome measurement outcome. Further since there wereno flags, an error E afflicting the data qubits must satisfy wt(E)≤t.Thus repeating the syndrome measurement using non-flag circuits willcorrectly identify and remove the error.

Note that if there are no flags, the protocol terminates when eitherCase 1 or Case 2 is satisfied. As was shown in Section IV, the maximumnumber of syndrome measurement rounds until either case is satisfied ist²+t+1.

Case 3: A set of t circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(t) )}flagged.

Since t circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(t) )} flagged and giventhat there can be at most t faults, then no other faults can occurduring the protocol. Hence, when repeating the syndrome measurementusing non-flag circuits, the measured syndrome will correspond to anerror E_(r)∈{tilde over (E)}^(t) _(t)(g_(i) ₁ , . . . g_(i) _(t) , s).Since from the flag t-FTEC condition all elements of Ē^(t) _(t)(g_(i) ₁, . . . g_(i) _(t) ,s) are logically equivalent, the product of errorsresulting from the flag circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(t) )}will be corrected.

Note that for an input error E_(in) of arbitrary weight and bydefinition of Ē^(t) _(t)(g_(i) ₁ , . . . g_(i) _(t) ,s), the correctedstate will always be a valid codeword. Thus both conditions ofDefinition 2 are satisfied.

Case 4: The m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )} flagged with1≤m<t and n_(same)=t−m+1

Suppose that at some point during the protocol there were m circuits{C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )} that flagged. There can thus be atmost t−m faults that don't result in a flag. When repeating the syndromemeasurement using flag circuits, if the same syndrome is measured t−m+1times in a row, it is guaranteed that at least one of the syndromemeasurement was fault-free and thus correctly identified the errorsarising from the flags (along with errors E with wt(E)≤t−m). There areseveral possibilities for the distribution of the errors.

-   -   1. There were t−m benign faults that occurred during a syndrome        measurement and each circuit in {C(g_(i) ₁ ), . . . ,C(g_(i)        _(m) )} had a fault at a bad location.    -   2. There were t faults distributed throughout the {C(g_(i) ₁ ),        . . . ,C(g_(i) _(m) )} flag circuits.    -   3. There were j₁<t−m in faults that did not lead to a flag and        j₂≥m (with j₁+j₂≤t) faults which caused the circuits {C(g_(i) ₁        ), . . . ,C(g_(i) _(m) )} to flag.

All possible error outcomes are included in the set ∪^(t−m)_(j=0)Ē^(t−j) _(t)C(g_(i) ₁ ), . . . ,C(g_(i) _(m) ,s). Since from theflag t-FTEC condition these can be identified and corrected, the outputstate can differ from a valid codeword by an error of at most weightt−m.

Case 5: The m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )} flagged with1≤m<t and n_(diff)=t−m

If m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )} flagged, there can beat most t−m faults that do not lead to a flag. If n_(diff)=t−m, thenthere must have been exactly t−m faults that did not lead to a flag.Repeating the syndrome measurement using non-flag circuits and from theflag t-FTEC condition, the syndrome will correspond to an error in theset {tilde over (E)}^(m) _(t)(g_(i) ₁ , . . . g_(i) _(m) ,s) thusremoving the errors. If the input state differs from a valid codeword byan error of arbitrary weight, by definition of {tilde over (E)}^(m)_(t)(g_(i) ₁ , . . . g_(i) _(m) ,s) the output state will be a validcodeword.

Case 6: The m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )} flagged with1≤m<t, n_(diff)=k; m+k<t and n_(same)=t−m−k+1

In this case there are m flags, k faults which caused the syndromes tochange and t−m−k+1 identical syndromes after all the m flags occurred.Since there can only be t−m−k errors which don't change the syndrome, atleast one syndrome measurement (say during round r with syndrome s) willbe error free correctly identifying the errors afflicting the dataduring round r. It is straightforward to verify that the possible errorscorresponding to the measured syndrome s belong to the set ∪^(t−m−k)_(j=0){tilde over (E)}^(t−j−k) _(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s).

After applying a correction, there can be an error of weight at mostt−m−k on the data.

VIII. Fault-Tolerant State Preparation and Measurement using Flag t-FTEC

In this section, it is shown how to fault-tolerantly prepare a logical|0

state and how to perform fault-tolerant measurements for codes thatsatisfy the flag t-FTEC condition of Section IV. Note that there areseveral methods that can be used for doing so. Here, a procedure isfollowed similar to that shown in D. Gottesman, “An introduction toquantum error correction and fault-tolerant quantum computation,”Proceedings of Symposia in Applied Mathematics, vol. 68, pp. 13-58(2010) when performing Shor EC. However, as was already shown, thedisclosed example protocol requires fewer syndrome measurementrepetitions than Shor EC.

Consider an n-qubit stabilizer code C with stabilizer group S=

g₁, . . . ,g_(n−k)

that can correct up to t errors. Notice that the encoded |0

state is a +1 eigenstate of the logical Z operator and all of the codesstabilizer generators. For k encoded qubits, |0

would be +1 eigenstate of {Z ₁, . . . Z _(k)} and all of the codesstabilizers. For notational simplicity in what follows, it is assumedthat k=1.

The state |0

is a stabilizer state completely specified by the full stabilizergenerators of S and Z. One can think of S′=

g₁, . . . g_(n−1),Z

as a stabilizer code with zero encoded qubits and a 2⁰=1 dimensionalHilbert space. Thus any state which is a +1 eigenstate of all operatorsin S′ will correspond to the encoded |0

state.

Now, suppose one prepares |0

_(in) using a non-fault-tolerant encoding and perform flag t-FTEC usingthe extended stabilizers

g₁, . . . g_(n−1),Z

. Then by the second criteria of Definition 2, the output state |0

_(out) is guaranteed to be a valid codeword with at most t single-qubiterrors. But for the extended stabilizers

g₁, . . . g_(n−1),Z

there is only one valid codeword which corresponds to the encoded |0

state. In fact, by the second criteria of Definition 2, any n-qubitinput state prepared using non-fault-tolerant circuits is guaranteed tobe an encoded |0

state if there are no more than t faults in the EC round.

Here, it is pointed out that the flag t-FTEC condition of Section IV Ais trivially satisfied for S′ since the codes logical operators are nowstabilizers. In other words, if two errors belong to the set {tilde over(E)}^(m) _(t)(g_(i) ₁ , . . . ,g_(i) _(k) ,s), then their product willalways be a stabilizer. Therefore, flag t-FTEC protocol can always beapplied for the code S′.

To summarize, the encoded |0

state can be prepared by first preparing any n-qubit state usingnon-fault-tolerant circuits followed by applying flag t-FTEC using theextended stabilizers

g₁, . . . g_(n−1),Z

. This guarantees that the output state will be the encoded |0

state with at most t single-qubit errors.

Now, suppose one wants to measure the eigenvalue of a logical operator Pwhere P is a Pauli. If C is a CSS code, one could measure the eigenvalueby performing the measurement transversally. So suppose C is not a CSScode. From D. Gottesman, “An introduction to quantum error correctionand fault-tolerant quantum computation,” Proceedings of Symposia inApplied Mathematics, vol. 68, pp. 13-58 (2010), it is understood thatperforming a measurement with s faults on an input state with r errors(r+s≤t) is equivalent to correcting the r errors and performing themeasurement perfectly. The protocol for fault-tolerantly measuring theeigenvalue of P is described as follows:

-   -   1. Perform flag t-FTEC.    -   2. Use a circuit in FIG. 8 once to measure the eigenvalue of P.    -   3. Repeat steps 1 and 2 2t+1 times and take the majority of the        eigenvalue of P.

Step 1 is used to remove input errors to the measurement procedure.However during error correction, a fault can occur which could cause anew error on the data. Thus by repeating the measurement withoutperforming error correction, the wrong state would be measured each timeif there were no more faults. But repeating the syndrome 2t+1 times, itis guaranteed that at least t+1 of the syndrome measurements had nofaults and that the correct eigenvalue of P was measured. Thus takingthe majority of the measured eigenvalues will give the correct answer.

Note that during the fault-tolerant measurement procedure, if there is aflag either during the error correction round or during the measurementof P, when error correction is performed one corrects based on thepossible set of errors resulting from the flag.

IX. Quantum Reed-Muller Codes

In this section, it is first described how to construct the family ofquantum Reed-Muller codes QRM(m) with code parameters

2^(m)−1, k=1, d=3

following J. T. Anderson et al., “Fault-tolerant conversion between thesteane and reed-muller quantum codes,” Phys. Rev. Lett., vol. 113, p.080501 (2014). It is then shown that the family of QRM(m) codes satisfythe sufficient flag 1-FTEC condition of Section IV C.

Reed-Muller codes of order m (RM(1, m)) are defined recursively from thefollowing generator matrices: First, RM(1, 1) has generator matrix

$\begin{matrix}{{G_{1} = \begin{pmatrix}1 & 1 \\0 & 1\end{pmatrix}},} & (10)\end{matrix}$and RM(1, m+1) has generator matrix

$\begin{matrix}{{G_{m + 1} = \begin{pmatrix}G_{m} & G_{m} \\0 & 1\end{pmatrix}},} & (11)\end{matrix}$where 0 and 1 are vectors of zeros and ones in Eq. (11). The dual ofRM(1, m+1) is given by the higher order Reed-Muller code RM(m−2, m). Ingeneral, the generator matrices for higher-order Reed-Muller codes RM(r,m) are given by

$\begin{matrix}{H_{r,{m + 1}} = {\begin{pmatrix}H_{r,m} & H_{r,m} \\0 & H_{{r - 1},m}\end{pmatrix}.{with}}} & (12) \\{{H_{2,1} = {H_{1,1} = \begin{pmatrix}1 & 1 \\0 & 1\end{pmatrix}}},} & (13)\end{matrix}$

The X stabilizer generators of QRM(m) are derived from shortenedReed-Muller codes where the first row and column of G_(m) are deleted.The resulting generator matrix is defined as G _(m). The Z stabilizergenerators are obtained by deleting the first row and column ofH_(m−2,m). Similarly, the resulting generator matrix is defined as H_(m−2,m).

As was shown in J. T. Anderson et al., “Fault-tolerant conversionbetween the steane and reed-muller quantum codes,” Phys. Rev. Lett.,vol. 113, p. 080501 (2014), rows(G _(m))⊂rows(H _(m−2,m)) and each rowhas weight 2^(m−1). Therefore, all the X-type stabilizer generators ofQRM(m) have corresponding Z-type stabilizers. By construction, theremaining rows of H _(m−2,m) will have weight 2^(m−2).

By construction, every weight 2^(m−2) row has support contained withinsome weight 2^(m−1) row of the generator matrix H _(m−2,m). Therefore,every Z-type stabilizer generator has support within the support of an Xgenerator.

X. Implementation of Steane Error Correction

FIG. 13(a) is a schematic block diagram 1300 showing a fault-tolerantSteane error correction circuit which can be applied to CSS codes. Eachline represents an encoded qubit. The circuit uses only two encoded |0

and |+

ancilla states (encoded in the same error correcting code which protectsthe data) to ensure that faults in the preparation circuits of theancilla's don't spread to the data block. FIG. 13(b) is a schematicblock diagram 1302 showing a fault-tolerant Steane error correctioncircuit which can be used for any CSS stabilizer code encoding the data.There are a total of eight encoded ancilla qubits instead of four. Thedark bold lines represent resting qubits.

TABLE V Pseudo-threshold results for the Full Steane and flagthree-qubit error correction schemes applied to the

 19, 1, 5 

 code. Since the Steane error correction protocol is non-deterministic,the number of qubits will depend on how many times the encoded statesare rejected. For low error rates, the states are accepted with highprobability so that the average number of qubits is ≈171. The examplethree quint flag error correction protocol requires at most four roundsof syndrome measurements, with each round requiring 162 time steps.However, for low noise rates, the average number of time steps will beclose to 162. FTEC scheme Noise model Number of qubits Time steps(T_(time)) Pseudo-threshold Full Steane-EC {tilde over (p)} = p ≥171 15p_(pseudo) = (3.50 ± 0.14) × 10⁻³ Full Steane-EC {tilde over (p)} =p/100 ≥171 15 p_(pseudo) = (1.05 ± 0.04) × 10⁻³ Flag-EC 

 19, 1, 5 

{tilde over (p)} = p 22 162 ≤ T_(time) ≤ 648 p_(pseudo) = (1.14 ± 0.02)× 10⁻⁵ Flag-EC 

 19, 1, 5 

{tilde over (p)} = p/100 22 162 ≤ T_(time) ≤ 648 p_(pseudo) = (7.74 ±0.16) × 10⁻⁵

In this section, a description is provided as to how to implement Steaneerror correction and discuss its fault-tolerant properties. Alsoprovided is a comparison of a version of Steane error correction withthe fault-tolerant scheme described in Section III B applied to the

19, 1, 5

code.

Steane error correction is a fault-tolerant scheme that applies to theCalderbank-Shor-Steane (CSS) family of stabilizer codes. See A. W.Steane, “Active stabilization, quantum computation, and quantum statesynthesis,” Phys. Rev. Lett., vol. 78, no. 11, p. 2252 (1997). In Steaneerror correction, the idea is to use encoded |0

and |+

=(|0

+|1

)/√{square root over (2)} ancilla states to perform the syndromeextraction. The ancilla's are encoded in the same error correcting codethat is used to protect the data. The X stabilizer generators aremeasured by preparing the encoded |0

state and performing transversal CNOT gates between the ancilla and thedata, with the ancilla acting as the control qubits and the data actingas the target qubits. After applying the transversal CNOT gates, thesyndrome is obtained by measuring |0

transversally in the X-basis. The code construction for CSS codes iswhat guarantees that the correct syndrome is obtained after applying atransversal measurement (see D. Gottesman, “An introduction to quantumerror correction and fault-tolerant quantum computation,” Proceedings ofSymposia in Applied Mathematics, vol. 68, pp. 13-58 (2010) for moredetails).

Similarly, the Z-stabilizer generators are measured by preparing theencoded |+

, applying CNOT gates transversally between the ancilla and the datawith the data acting as the control qubits and the ancilla's acting asthe target qubits. The syndrome is then obtained by measuring |+

transversally in the Z-basis.

The above protocol as stated is not sufficient in order to befault-tolerant. The reason is that in general the circuits for preparingthe encoded |0

and |+

are not fault-tolerant in the sense that a single error can spread to amulti-weight error which could then spread to the code-block whenapplying the transversal CNOT gates. To make the protocolfault-tolerant, extra |0

and |+

ancilla states (which is sometimes referred to as a “verifier qubits”)are needed to check for multi-weight errors at the output of the ancillastates.

Logical failure rate of the full fault-tolerant Steane error correctionapproach of FIG. 13(b) and the example flag FTEC protocol of Section IIIB applied to the

19, 1, 5

code. In schematic block diagram 1400 of FIG. 14(a), resting qubits arechosen to fail with a total probability {tilde over (p)}=p while inschematic block diagram 1402 of FIG. 14(b), resting qubits fail withprobability {tilde over (p)}=p/100. The intersection between the dashedcurve and solid lines represent the pseudo-threshold of both errorcorrection schemes.

For the |0

ancilla, multiple X errors can spread to the data if left unchecked.Therefore, another encoded |0

ancilla is prepared and a transversal CNOT gate is applied between thetwo states with the ancilla acting as the control and the verifier stateacting as target. Anytime X errors are detected the state is rejectedand the error correction protocol start over. Further, if the verifierqubit measures a −1 eigenvalue of the logical Z operator, the ancillaqubit is also rejected. A similar technique is used for verifying the |+

state (see FIG. 13(a)).

For the

7, 1, 3

Steane code, an error E=Z_(i)Z_(j) can always be written as E=ZZ_(k)where Z is the logical Z operator (this is not true for general CSScodes). But |0

is a +1 eigenstate of Z. Therefore, one doesn't need to worry about Zerrors of weight greater than one occurring during the preparation ofthe |0

state.

In P. Aliferis, D. Gottesman, and J. Preskill, “Quantum accuracythreshold for concatenated distance-3 codes,” Quant Inf. Comput., vol.6, pp. 97-165 (2006), it was shown that unlike for the

7, 1, 3

code, for general CSS codes the encoded ancilla states need to beverified for both X and Z errors in order for Steane error correction tosatisfy the fault-tolerant properties of Definition 2. An examplegeneral fault-tolerant scheme is shown in FIG. 13(b). In general, FIG.13(a) will only satisfy the fault-tolerant criteria of Definition 2 forperfect CSS codes (see P. Aliferis et al., “Quantum accuracy thresholdfor concatenated distance-3 codes,” Quant. Inf. Comput., vol. 6, pp.97-165 (2006) for more details).

In Section V B logical failure rates were computed for Steane errorcorrection applied to the

19, 1, 5

code using the circuit of FIG. 13(a) in order to minimize the number ofphysical qubits. However, since the

19, 1, 5

code is not a perfect CSS code, only the circuit in FIG. 13(b) satisfiesall the criteria of Definition 2. This explains why the leading ordercontributions to the logical failure was of the form p_(L)=c₁p²+c₂p³+

(p⁴) instead of p_(L)=cp³+

(p⁴) (which would be the case for a distance-5 code).

In FIG. 14, Steane error correction was applied using the circuit ofFIG. 13(b) to achieve the full error correcting capabilities of the

19, 1, 5

code. Methods presented in A. Paetznick and B. W. Reichardt,“Fault-tolerant ancilla preparation and noise threshold lower bounds forthe 23-qubit golay code,” Quant. Inf. Compt., vol. 12, pp. 1034-1080(2011); C. Chamberland et al., “Overhead analysis of universalconcatenated quantum codes,” Phys. Rev. A, vol. 95, p. 022313 (2017),were used in order to obtain the encoded |0

state (since the

19, 1, 5

code is self-dual, the |+

state is obtain by interchanging all physical |0

and |+

states are reversing the direction of the cnot gates). The results arecompared with our flag FTEC scheme of Section III B for the noise modelswhere resting qubits fail with probability {tilde over (p)}=p and {tildeover (p)}=p/100. In both cases the logical failure rates have a leadingorder p³ contribution (which is determined from finding the best fitcurve to the data). The pseudo-threshold results are given in Table VI.

As can be seen, the full Steane error correction protocol of FIG. 13(b)achieves significantly lower logical failure rates compared to using thecircuit in FIG. 13(a) at the cost of using a minimum of 171 qubitscompared to 95. In contrast, the FTEC scheme of Section III B has apseudo-threshold that is one to two orders of magnitude lower than thanthe full EC scheme but requires only 22 qubits.

XI. Implementation of Surface Code Error Correction

The rotated surface code is also considered in S. Bravyi and A. Kitaev,“Quantum codes on a lattice with boundary,” arXiv:quant-ph/9811052(1998); E. Dennis et al., “Topological quantum memory,” Journal ofMathematical Physics, vol. 43, pp. 4452-4505 (2002); A. G. Fowler etal., “Surface codes: Towards practical large-scale quantum computation,”Phys. Rev. A, vol. 86, p. 032324 (2012); Y. Tomita and K. M. Svore,“Low-distance surface codes under realistic quantum noise,” Phys. Rev.A., vol. 90, p. 062320 (2014); X.-G. Wen, “Quantum orders in an exactsoluble model,” Phys. Rev. Lett., vol. 90, p. 016803 (January 2003). asshown in FIG. 15, which has n=d² data qubits for distance d. Althoughthere is concern with error correction under the circuit level noisemodel described in Section II B, it is useful to build intuition byfirst considering the idealized noise model in which stabilizermeasurements are perfect, and single qubit X errors occur withprobability 2p/3 (Z errors can be treated in the same way). An X typeerror E occurs with probability

(p^(wt(E))), and has syndrome s(E).

More specifically, FIG. 15(a) is a schematic block diagram 1500 showingthe d=3 surface code, with data qubits represented by white circles. TheX (Z) stabilizer generators are measured with measurement ancillas(gray) in red (green) faces (also denoted as “red” and “r” for red, or“green” for green). Block diagram 1502 is a diagram for perfectingmeasurements, the graph G_(2D) used to correct X type errors (here ford=5) consists of a black node for each Z-stabilizer, and a black edgefor each data qubit in the surface code. White boundary nodes and blueboundary edges are added. Black and blue edges are given weight one andzero respectively. In this example, a two qubit X error has occurredcausing three stabilizers to be violated (red nodes). A boundary node isalso highlighted and a minimum weight correction (red edges) whichterminates on highlighted nodes is found. The algorithm succeeds as theerror plus correction is a stabilizer.

The minimum weight X-type correction can be found efficiently for thesurface code in terms of the graph G_(2D) shown in FIG. 15(b). The graphG_(2D) has a bulk node (black circle) for each Z stabilizer generator,and a bulk edge (black) for each data qubit. A bulk edge coming from abulk node corresponds to the edge's data qubit being in the support ofthe node's stabilizer. The graph also contains boundary nodes (whiteboxes) and boundary edges (blue), which do not correspond to stabilizersor data qubits. Each bulk and boundary edge is assigned weight one andzero respectively. The minimum weight decoder is then implemented asfollows. After the error E is applied, the nodes corresponding tounsatisfied stabilizers are highlighted. If an odd number of stabilizerswas unsatisfied, one of the boundary nodes is also highlighted.Highlighted nodes are then efficiently paired together by the minimumweight connections in the graph, by Edmonds' algorithm (see, e.g., J.Edmonds, “Paths, trees, and flowers,” Canadian Journal of mathematics,vol. 17, no. 3, pp. 449-467 (1965); V. Kolmogorov, “Blossom V: a newimplementation of a minimum cost perfect matching algorithm,”Mathematical Programming Computation, vol. 1, no. 1, pp. 43-67 (2009)).The correction C is applied to the edges in the connection. Note thatany single

(p) fault in this noise model corresponds to a weight one edge on thegraph.

For circuit noise, one can introduce a measurement qubit for eachstabilizer generator, as represented by gray circles in FIG. 15, andcircuits must be specified to implement the measurements, such as thosein FIG. 16. More specifically, FIG. 16 shows circuits for measuring, inschematic block diagram 1600 and FIG. 16 (a), a Z-type generator, and inschematic block diagram 1602 and FIG. 16(b), an X-type generator.Identity gates (black rectangles) are inserted in the Z-type stabilizermeasurement circuits to ensure that all measurements are synchronized.Note that unlike in A. G. Fowler et al., “Surface codes: Towardspractical large-scale quantum computation,” Phys. Rev. A, vol. 86, p.032324 (2012), to be consistent with the other schemes in thisdisclosure, one can assume that one can prepare and measure in both theX and Z basis. The performance of the code is sensitive to the choice ofcircuit Y. Tomita and K. M. Svore, “Low-distance surface codes underrealistic quantum noise,” Phys. Rev. A., vol. 90, p. 062320, (2014), forexample a poor choice could allow a single fault to cause a logicalfailure for d=3 for any choice of decoder.

To implement the decoder, first construct a new three dimensional graphG_(3D) by stacking d copies of the planar graph G_(2D) that was shown inFIG. 15(b), and adding new bulk (boundary) edges to connect bulk(boundary) nodes in neighboring layers. Also added are additionaldiagonal edges such that any single

(p) fault in the measurement circuits corresponds to a weight-one edgein G_(3D) (see FIG. 17). For simplicity, further possible optimizationsare not involved, such as setting edge weights based on preciseprobabilities and including X-Z correlations. FIG. 17 is a block diagram1700 showing examples of a single fault leading to diagonal edges inG_(3D). Dark arrows represent the CNOT sequence. More specifically, FIG.17(a) illustrates an X error occurs during the third time step in theCNOT gate acting on the central data qubit. FIG. 17(b) illustrates thatduring the fifth time step of this round, the X error is detected by theZ type measurement qubit to the top right. FIG. 17(c) illustrates thatthe X error is not detected by the bottom left Z type stabilizer untilthe following round. FIG. 17(d) illustrates that an XX error occurs onthe third CNOT of an X measurement circuit, which is detected by the Zmeasurement to the right. FIG. 17(e) illustrates that detection by theleft Z stabilizer does not occur until the next round. FIG. 17(f)illustrates that the corresponding edges in G_(3D), green for (a-c), andblue for (d-e). Here, it is shown that two rounds of the graph ignoringboundary edges.

All simulations of the surface code are performed using the circuitnoise model in Section II B, with the graph G_(3D) described above asfollows (to correct X errors):

-   -   1. Data acquisition: Stabilizer outcomes are stored over d        rounds of noisy error correction, followed by one round of        perfect error correction. The net error E applied over all d        rounds is recorded.    -   2. Highlight nodes: Nodes in the graph G_(3D) are highlighted if        the corresponding Z-type stabilizer outcome changes in two        consecutive rounds. (For an odd number of highlighted vertices,        highlight the boundary vertex.)    -   3. Minimum weight matching: Find a minimal edge set forming        paths that terminate on highlighted nodes. Highlight the edge        set.    -   4. Vertical collapse: The highlighted edges in G_(3D) are mapped        edges in the planar graph G_(2D), and are then added modulo 2.    -   5. Correction: The X-type correction C_(x) is applied to        highlighted edges in G_(2D).        The Z correction C_(z) is found analogously. Finally, if the        residual Pauli R=EC_(x)C_(z) is a logical operator, one can say        the protocol succeeded, otherwise it is considered to have        failed.

XII. Compact Implementation of Flag Error Correction

FIG. 18 is a schematic block diagram 1800 illustrating a circuit formeasuring the Z stabilizer generators of the

7, 1, 3

code using one flag qubit and three measurement qubits. The circuit isconstructed such that any bad location leading to a bad error willresult in a flag, and all bad errors have a unique syndrome.

In R. Chao and B. W. Reichardt, “Quantum error correction with only twoextra qubits,” arXiv:quant-ph/1705.02329 (2017), it was shown that byusing extra ancilla qubits in the flag-EC protocol, it is possible tomeasure multiple stabilizer generators during one measurement cyclewhich could reduce the circuit depth. Note that for the Steane code,measuring the Z stabilizers using FIG. 2 requires only one extra timestep. In this section, logical failure rates of the

7, 1, 3

code are compared using the flag-EC method of Section III A whichrequires only two ancilla qubits and a flag-EC method which uses fourancilla qubits but that can measure all Z stabilizer generators in onecycle (see FIG. 18). All X stabilizers are measured in a separate cycle.All simulations were performed using the noise model and methods ofSection II B.

FIG. 19 is a graph 1900 showing logical failure rates of flag-ECprotocols using two and four ancilla qubits applied to the

7, 1, 3

Steane code.

Logical failure rates for {tilde over (p)}=p are shown in FIG. 19.Pseudo-thresholds and the number of time steps required to implement theprotocols are given in Table VI. Note that measuring stabilizers usingtwo ancilla's requires at most two extra time steps. Furthermore, theextra ancilla's for measuring multiple stabilizers result in more idlequbit locations compared to using only two ancilla qubits. With theadded locations for errors to be introduced, the flag error correctionprotocol using only two ancilla's achieves a higher pseudo-thresholdcompared to the protocol using more ancilla's. Thus assuming thatreinitializing qubits can be done without introducing many errors intothe system, FTEC using fewer qubits could achieve lower logical failurerates compared to certain schemes using more qubits.

TABLE VI Pseudo-thresholds and circuit depth for flag-EC protocols usingtwo and four ancilla qubits applied to the 

 7, 1, 3 

 code. The results are presented for the noise models where p = p and p= p/100. FTEC scheme Noise model Number of qubits Time steps (T_(time))Pseudo-threshold Flag-EC 

 7, 1, 3 

{tilde over (p)} = p 9 36 ≤ T_(time) ≤ 108 p_(pseudo) = (3.39 ± 0.10) ×10⁻⁵ Flag-EC 

 7, 1, 3 

11 34 ≤ T_(time) ≤ 104 p_(pseudo) = (2.97 ± 0.01) × 10⁻⁵

TABLE VII Stabilizer generators for the 5-qubit code, including d = 3, d= 5 ( 

 19, 1, 5 

 code) and d = 5 ( 

 17, 1, 5 

 code) family of color codes. The last row illustrates representativesof the codes logical operators.

 5, 1, 3 

Steane code

 19, 1, 5 

 code

 17, 1, 5 

 code X₁Z₂Z₃X₄ Z₄Z₅Z₆Z₇ Z₁Z₂Z₃Z₄, X₁X₂X₃X₄ Z₁Z₂Z₃Z₄, X₁X₂X₃X₄ X₂Z₃Z₄X₅Z₂Z₃Z₆Z₇ Z₁Z₃Z₅Z₇, X₁X₃X₆X₇ Z₁Z₃Z₅Z₆, X₁X₃X₅X₆ X₁X₃Z₄Z₅ Z₁Z₃Z₅Z₇Z₅Z₇Z₈Z₁₁Z₁₂Z₁₃, X₅X₇X₈X₁₁X₁₂X₁₃ Z₅Z₆Z₉Z₁₀, X₅X₆Z₉Z₁₀ Z₁X₂X₄Z₅ X₄X₅X₆X₇Z₁Z₂Z₅Z₆Z₈Z₉, X₁X₂X₅X₆X₈X₉ Z₇Z₈Z₁₁Z₁₂, X₇X₈X₁₁X₁₂ X₂X₃X₆X₇ X₆Z₉Z₁₆Z₁₉,X₆X₉X₁₆X₁₉ Z₉Z₁₀Z₁₃Z₁₄, X₉X₁₀X₁₃X₁₄ X₁X₃X₅X₇ Z₁₆Z₁₇Z₁₈Z₁₉, X₁₆X₁₇X₁₈X₁₉Z₁₁Z₁₂Z₁₅Z₁₆, X₁₁X₁₂X₁₅X₁₆ Z₈Z₉Z₁₀Z₁₁Z₁₆Z₁₇, X₈X₉X₁₀X₁₁X₁₆X₁₇Z₈Z₁₂Z₁₆Z₁₇, X₈X₁₂Z₁₆Z₁₇ Z₁₀Z₁₁Z₁₂Z₁₅, X₁₀X₁₁X₁₂X₁₅ Z₃Z₄Z₆Z₇Z₁₀Z₁₁Z₁₄Z₁₅Z₁₂Z₁₃Z₁₄Z₁₅, X₁₂X₁₃X₁₄X₁₅ X₃X₄X₆X₇X₁₀X₁₁X₁₄X₁₅ X = X^(⊗5), Z = Z^(⊗5) X= X^(⊗7), Z = Z^(⊗7) X = X^(⊗19), Z = Z^(⊗19) X = X^(⊗17), Z = Z^(⊗17)

XIII. Stabilizer Generators of Various Codes

In Table VII, stabilizer generators are provided for the

5, 1, 3

code,

7, 1, 3

Steane code,

19, 1, 5

and

17, 1, 5

color codes.

XIV. Further Representative Embodiments

Among the embodiments disclosed herein are methods for performing flagfault-tolerant error correction with arbitrary distance codes. Furtherembodiments as disclosed herein include quantum circuits comprising anyof the quantum devices for performing the flag fault-tolerant errorcorrection techniques.

FIG. 24 is a flowchart 2400 illustrating a technique for operating aquantum system in accordance with embodiments of the disclosedtechnology. In particular, the illustrated flowchart 2400 illustrates amethod to for implementing an error correction protocol in a quantumcomputing device in accordance with embodiments of the disclosedtechnology. The illustrated embodiment should not be construed aslimiting, as the disclosed method acts can, in some cases, be performedalone, in different orders, or at least partially simultaneously withone another. Further, any of the disclosed methods or method acts can beperformed with any other methods or method acts disclosed herein.

At 2410, logical operators of a stabilizer code are enumerated (e.g., a[[n,k,d]] stabilizer code).

At 2412, sets of (d−1)/2 stabilizers are enumerated and a determinationis made as whether any logical operators are contained in joint supportof (d−1)/2 stabilizers. If so, then an error correction protocol isapplied using standard circuits (e.g., as shown in Section III C);otherwise, the procedure continues at 2416.

At 2416, standard t-flagged circuits for each stabilizer are tried and adetermination is made as to whether Flagged t-FTEC conditions aresatisfied. If the conditions are satisfied, then an error correctionprotocol as disclosed herein is applied (e.g., as in Section IV) at2418; otherwise, the procedure continues at 2420.

At 2420, different t-flagged circuits for each stabilizer are repeatedlytried (e.g., using n different circuit, where n is any integer value).For the different circuits, a determination is made as to whether thereare circuits for each stabilizer that satisfy the flagged t-FTECconditions. If the conditions are satisfied, then an error correctionprotocol as disclosed herein is applied (e.g., as in Section IV) at2418; otherwise, the procedure terminates at 2422 because an errorcorrection protocol could not be applied.

FIG. 25 is a flowchart 2500 illustrating a technique for implementing anerror correction protocol in a quantum computing device in accordancewith embodiments of the disclosed technology. The illustrated embodimentshould not be construed as limiting, as the disclosed method acts can,in some cases, be performed alone, in different orders, or at leastpartially simultaneously with one another. Further, any of the disclosedmethods or method acts can be performed with any other methods or methodacts disclosed herein.

At 2510, a quantum operation is performed in a quantum circuitimplemented in the quantum computing device.

At 2512, a fault-tolerant error correction protocol is performed usingonly a single ancilla qubit and an error-code distance of 3.

In particular implementations, the fault-tolerant error correctionprotocol performs syndrome measurements at most three times. In someimplementations, the performing the fault-tolerant error correctionprotocol comprises repeating an error syndrome measurement of theancilla qubit until one of multiple criteria (e.g., 3 criteria) issatisfied. In particular implementations, the performing thefault-tolerant error correction protocol comprises repeating an errorsyndrome measurement of a flag circuit comprising the ancilla qubituntil one of the following is satisfied: (a) if the syndrome s isrepeated twice in a row and there were no flags, apply the correctionmin wt(s); (b) if there were no flags and the syndromes s₁ and s₂ fromtwo consecutive rounds differ, repeat the syndrome measurement usingnon-flag circuits yielding syndrome s, apply the correction min wt(s);and/or (c) if a circuit C(g_(i)) flags, stop and repeat the syndromemeasurement using non-flag circuits yielding syndrome s, apply acorrection from {tilde over (E)}(g_(i),s).

FIG. 26 is a flowchart 2600 illustrating a technique for implementing anerror correction protocol in a quantum computing device in accordancewith embodiments of the disclosed technology. The illustrated embodimentshould not be construed as limiting, as the disclosed method acts can,in some cases, be performed alone, in different orders, or at leastpartially simultaneously with one another. Further, any of the disclosedmethods or method acts can be performed with any other methods or methodacts disclosed herein.

At 2610, a quantum operation is performed in a quantum circuitimplemented in the quantum computing device.

At 2612, a fault-tolerant error correction protocol is performed usingonly two ancilla qubits and an error-code distance of 5.

In particular implementations, the fault-tolerant error correctionprotocol performs syndrome measurements at most seven times. In certainimplementations, the performing the fault-tolerant error correctionprotocol comprises repeating error syndrome measurements of the twoancilla qubits until one of multiple criteria (e.g., three) issatisfied.

In some implementations, the performing the fault-tolerant errorcorrection protocol further comprises tracking a number of timesconsecutive measurements are different and a number of times consecutivemeasurements are equal. Further, in some instances, the number of timesconsecutive measurements are different is stored in a first countern_(diff), and wherein the number of times consecutive measurements areequal is stored in a second counter n_(same). In one example, given asequence of consecutive syndrome measurement outcomes s_(k) and s_(k+1),the first counter and the second counter are modified according to a setof rules comprising: (a) if n_(diff)=0 and s_(k)≠s_(k+1), increasen_(diff) by one; (b) if n_(diff) didn't increase in the previous round,and s_(k)≠s_(k+1), increase n_(diff) by one; and/or (c) if a flagoccurred two rounds ago and s_(k)=s_(k+1), increase n_(same) by one. Incertain implementations, the performing the fault-tolerant errorcorrection protocol comprises repeating syndrome measurements using flagcircuits implemented by the two ancilla bits until one of the followingis satisfied: (a) if at any time a syndrome s is repeated 3 times in arow and there were no flags, apply the correction min wt(s); (b) ifn_(diff)=2 and there were no flags, repeat the syndrome using non-flagcircuits yielding syndrome s, apply the correction min wt(s); (c) if anytwo circuits C(g_(i)) and C(g_(j)) have flagged, repeat the syndromemeasurement using non-flag circuits yielding syndrome s, and apply acorrection from the set {tilde over (E)}² ₂(g_(i),g_(j),s); (d) if anycircuit C(g_(i)) has flagged and n_(diff)=1, repeat the syndrome usingnon-flag circuits yielding syndrome s, and apply a correction from theset {tilde over (E)}¹ ₂(g_(i),s); and/or (e) if any circuit C(g_(i)) hasflagged, n_(diff)=0 and n_(same)=1, use the measured syndrome s from thelast round, and apply a correction from the set {tilde over (E)}¹₂(g_(i),s)∪{tilde over (E)}² ₂(g_(i),s).

FIG. 27 is a flowchart 2700 illustrating a technique for implementing anerror correction protocol in a quantum computing device in accordancewith embodiments of the disclosed technology. The illustrated embodimentshould not be construed as limiting, as the disclosed method acts can,in some cases, be performed alone, in different orders, or at leastpartially simultaneously with one another. Further, any of the disclosedmethods or method acts can be performed with any other methods or methodacts disclosed herein.

At 2710, a quantum operation is performed in a quantum circuitimplemented in the quantum computing device.

At 2712, a fault-tolerant error correction protocol is performed usingone or more qubits and stabilizer codes of an arbitrary distance.

In some implementations, the performing the fault-tolerant errorcorrection protocol further comprises tracking a number of timesconsecutive measurements of the one or more qubits are different and anumber of times consecutive measurements of the one or more qubits areequal. For instance, in certain implementations, the number of timesconsecutive measurements are different is stored in a first countern_(diff), and wherein the number of times consecutive measurements areequal is stored in a second counter n_(same). For example, given asequence of consecutive syndrome measurement outcomes s_(k) and s_(k+1),the first counter and the second counter are modified according to a setof rules comprising: (a) if n_(diff)=0 and s_(k)≠s_(k+1), increasen_(diff) by one; (b) if n_(diff) didn't increase in the previous round,and s_(k)≠s_(k+1), increase n_(diff) by one; and/or (c) if a flagoccurred two rounds ago and s_(k)≠s_(k+1), increase n_(same) by one.Further, in certain implementations, the performing the fault-toleranterror correction protocol comprises repeating syndrome measurementsusing flag circuits implemented by the one or more ancilla bits untilone of the following is satisfied: (a) the same syndrome s is repeatedt+1 times in a row and there are no flags, apply the correction minwt(s); (b) there were no flags and n_(diff)=t, repeat the syndromemeasurement using non-flag circuits yielding the syndrome s, and applythe correction min wt(s); (c) some set of t circuits {C(g_(i) ₁ ), . . .,C(g_(i) _(t) )} have flagged, repeat the syndrome measurement usingnon-flag circuits yielding syndrome s, apply a correction from the set{tilde over (E)}^(t) _(t)(g_(i) ₁ , . . . g_(i) _(t) ,s); (d) some setof m circuits {C(g_(i) ₁ ), . . . ,C(g_(i) _(m) )} have flagged with1≤m<t and n_(same)=t−m+1, use the last measured syndrome s and apply acorrection from the set ∪^(t−m) _(j=0){tilde over (E)}^(t−j) _(t)(g_(i)₁ , . . . ,g_(i) _(m) ,s); (e) some set of m circuits {C(g_(i) ₁ ), . .. ,C(g_(i) _(m) )} have flagged with 1≤m<t and n_(diff)=t−m, repeat thesyndrome measurement using non-flag circuits yielding syndrome s, andapply a correction from the set {tilde over (E)}^(m) _(t)(g_(i) ₁ , . .. g_(i) _(m) ,s); and/or (f) some set of m circuits {C(g_(i) ₁ ), . . .,C(g_(i) _(m) )} have flagged with 1≤m<t, n_(diff)=k; m+k<t andn_(same)=t−m−k+1, use the syndrome s obtained during the last round andapply a correction from the set ∪^(t−m−k) _(j=0){tilde over (E)}^(t−j−k)_(t)(g_(i) ₁ , . . . ,g_(i) _(m) ,s).

XV. Example Computing Environments

FIG. 20 illustrates a generalized example of a suitable computingenvironment 2000 in which several of the described embodiments can beimplemented. The computing environment 2000 is not intended to suggestany limitation as to the scope of use or functionality of the disclosedtechnology, as the techniques and tools described herein can beimplemented in diverse general-purpose or special-purpose environmentsthat have computing hardware.

With reference to FIG. 20, the computing environment 2000 includes atleast one processing device 2010 and memory 2020. In FIG. 20, this mostbasic configuration 2030 is included within a dashed line. Theprocessing device 2010 (e.g., a CPU or microprocessor) executescomputer-executable instructions. In a multi-processing system, multipleprocessing devices execute computer-executable instructions to increaseprocessing power. The memory 2020 may be volatile memory (e.g.,registers, cache, RAM, DRAM, SRAM), non-volatile memory (e.g., ROM,EEPROM, flash memory), or some combination of the two. The memory 2020stores software 2080 implementing tools for synthesizing, generating, orcompiling one or more of the circuits as described herein.

The computing environment can have additional features. For example, thecomputing environment 2000 includes storage 2040, one or more inputdevices 2050, one or more output devices 2060, and one or morecommunication connections 2070. An interconnection mechanism (notshown), such as a bus, controller, or network, interconnects thecomponents of the computing environment 2000. Typically, operatingsystem software (not shown) provides an operating environment for othersoftware executing in the computing environment 2000, and coordinatesactivities of the components of the computing environment 2000.

The storage 2040 can be removable or non-removable, and includes one ormore magnetic disks (e.g., hard drives), solid state drives (e.g., flashdrives), magnetic tapes or cassettes, CD-ROMs, DVDs, or any othertangible non-volatile storage medium which can be used to storeinformation and which can be accessed within the computing environment2000. The storage 2040 can also store instructions for the software 2080implementing, generating, or synthesizing any of the describedtechniques, systems, or reversible circuits.

The input device(s) 2050 can be a touch input device such as a keyboard,touchscreen, mouse, pen, trackball, a voice input device, a scanningdevice, or another device that provides input to the computingenvironment 2000. The output device(s) 2060 can be a display device(e.g., a computer monitor, laptop display, smartphone display, tabletdisplay, netbook display, or touchscreen), printer, speaker, or anotherdevice that provides output from the computing environment 2000.

The communication connection(s) 2070 enable communication over acommunication medium to another computing entity. The communicationmedium conveys information such as computer-executable instructions orother data in a modulated data signal. A modulated data signal is asignal that has one or more of its characteristics set or changed insuch a manner as to encode information in the signal. By way of example,and not limitation, communication media include wired or wirelesstechniques implemented with an electrical, optical, RF, infrared,acoustic, or other carrier.

As noted, the various methods, circuit designs, or compilation/synthesistechniques for generating the disclosed circuits can be described in thegeneral context of computer-readable instructions stored on one or morecomputer-readable media. Computer-readable media are any available media(e.g., memory or storage device) that can be accessed within or by acomputing environment. Computer-readable media include tangiblecomputer-readable memory or storage devices, such as memory 2020 and/orstorage 2040, and do not include propagating carrier waves or signalsper se (tangible computer-readable memory or storage devices do notinclude propagating carrier waves or signals per se).

Various embodiments of the methods disclosed herein can also bedescribed in the general context of computer-executable instructions(such as those included in program modules) being executed in acomputing environment by a processor. Generally, program modules includeroutines, programs, libraries, objects, classes, components, datastructures, and so on, that perform particular tasks or implementparticular abstract data types. The functionality of the program modulesmay be combined or split between program modules as desired in variousembodiments. Computer-executable instructions for program modules may beexecuted within a local or distributed computing environment.

An example of a possible network topology 2100 (e.g., a client-servernetwork) for implementing a system according to the disclosed technologyis depicted in FIG. 21. Networked computing device 2120 can be, forexample, a computer running a browser or other software connected to anetwork 2112. The computing device 2120 can have a computer architectureas shown in FIG. 20 and discussed above. The computing device 2120 isnot limited to a traditional personal computer but can comprise othercomputing hardware configured to connect to and communicate with anetwork 2112 (e.g., smart phones, laptop computers, tablet computers, orother mobile computing devices, servers, network devices, dedicateddevices, and the like). In the illustrated embodiment, the computingdevice 2120 is configured to communicate with a computing device 2130(e.g., a remote server, such as a server in a cloud computingenvironment) via a network 2112. In the illustrated embodiment, thecomputing device 2120 is configured to transmit input data to thecomputing device 2130, and the computing device 2130 is configured toimplement circuit generation or compilation/synthesis methods forgenerating any of the disclosed circuits and outputting results to thecomputing device 2120. Any of the data received from the computingdevice 2130 can be stored or displayed on the computing device 2120(e.g., displayed as data on a graphical user interface or web page atthe computing devices 2120). In the illustrated embodiment, theillustrated network 2112 can be implemented as a Local Area Network(LAN) using wired networking (e.g., the Ethernet IEEE standard 802.3 orother appropriate standard) or wireless networking (e.g. one of the IEEEstandards 802.11a, 802.11b, 802.11g, or 802.11n or other appropriatestandard). Alternatively, at least part of the network 2112 can be theInternet or a similar public network and operate using an appropriateprotocol (e.g., the HTTP protocol).

Another example of a possible network topology 2200 (e.g., a distributedcomputing environment) for implementing a system according to thedisclosed technology is depicted in FIG. 20. Networked computing device2220 can be, for example, a computer running a browser or other softwareconnected to a network 2212. The computing device 2220 can have acomputer architecture as shown in FIG. 20 and discussed above. In theillustrated embodiment, the computing device 2220 is configured tocommunicate with multiple computing devices 2230, 2231, 2232 (e.g.,remote servers or other distributed computing devices, such as one ormore servers in a cloud computing environment) via the network 2212. Inthe illustrated embodiment, each of the computing devices 2230, 2231,2232 in the computing environment 2200 is used to perform at least aportion of a circuit generation or synthesis/compilation process forgenerating any of the disclosed circuits. In other words, the computingdevices 2230, 2231, 2232 form a distributed computing environment inwhich the generation/compilation/synthesis processes are shared acrossmultiple computing devices. The computing device 2220 is configured totransmit input data to the computing devices 2230, 2231, 2232, which areconfigured to distributively implement such as process, includingperformance of any of the disclosed methods or creation of any of thedisclosed circuits, and to provide results to the computing device 2220.Any of the data received from the computing devices 2230, 2231, 2232 canbe stored or displayed on the computing device 2220 (e.g., displayed asdata on a graphical user interface or web page at the computing devices2220). The illustrated network 2212 can be any of the networks discussedabove with respect to FIG. 21.

With reference to FIG. 23, an exemplary system for implementing thedisclosed technology includes computing environment 2300. In computingenvironment 2300, a compiled quantum computer circuit descriptionincluding any of the disclosed quantum circuits in accordance with anyof the disclosed embodiments can be used to program (or configure) oneor more quantum processing units such that the quantum processingunit(s) implement the circuit described by the quantum computer circuitdescription. The quantum computer circuit description can implement anyof the disclosed circuits.

The environment 2300 includes one or more quantum processing units 2302and one or more readout device(s) 2308. The quantum processing unit(s)execute quantum circuits that are precompiled and described by thequantum computer circuit description. The quantum processing unit(s) canbe one or more of, but are not limited to: (a) a superconducting quantumcomputer; (b) an ion trap quantum computer; (c) a fault-tolerantarchitecture for quantum computing; and/or (d) a topological quantumarchitecture (e.g., a topological quantum computing device usingMajorana zero modes). The precompiled quantum circuits, including any ofthe disclosed circuits, can be sent into (or otherwise applied to) thequantum processing unit(s) via control lines 2306 at the control ofquantum processor controller 2320. The quantum processor controller (QPcontroller) 2320 can operate in conjunction with a classical processor2310 (e.g., having an architecture as described above with respect toFIG. 20) to implement the desired quantum computing process and toimplement any of the disclosed error-correction protocols as disclosedherein. In the illustrated example, the QP controller 2320 furtherimplements the desired quantum computing process along with any of thedisclosed error-correction protocols via one or more QP subcontrollers2304 that are specially adapted to control a corresponding one of thequantum processor(s) 2302. For instance, in one example, the quantumcontroller 2320 facilitates implementation of the compiled quantumcircuit by sending instructions to one or more memories (e.g.,lower-temperature memories), which then pass the instructions tolow-temperature control unit(s) (e.g., QP subcontroller(s) 2304) thattransmit, for instance, pulse sequences representing the gates to thequantum processing unit(s) 2302 for implementation. In other examples,the QP controller(s) 2320 and QP subcontroller(s) 2304 operate toprovide appropriate magnetic fields, encoded operations, or other suchcontrol signals to the quantum processor(s) to implement the operationsof the compiled quantum computer circuit description. The quantumcontroller(s) can further interact with readout devices 2308 to helpcontrol and implement the desired quantum computing process (e.g., byreading or measuring out data results from the quantum processing unitsonce available, etc.)

With reference to FIG. 23, compilation is the process of translating ahigh-level description of a quantum algorithm into a quantum computercircuit description comprising a sequence of quantum operations orgates, which can include the circuits as disclosed herein. Thecompilation can be performed by a compiler 2322 using a classicalprocessor 2310 (e.g., as shown in FIG. 20) of the environment 2300 whichloads the high-level description from memory or storage devices 2312 andstores the resulting quantum computer circuit description in the memoryor storage devices 2312.

In other embodiments, compilation can be performed remotely by a remotecomputer 2300 (e.g., a computer having a computing environment asdescribed above with respect to FIG. 20) which stores the resultingquantum computer circuit description in one or more memory or storagedevices 2362 and transmits the quantum computer circuit description tothe computing environment 2300 for implementation in the quantumprocessing unit(s) 2302. Still further, the remote computer 2300 canstore the high-level description in the memory or storage devices 2362and transmit the high-level description to the computing environment2300 for compilation and use with the quantum processor(s). In any ofthese scenarios, results from the computation performed by the quantumprocessor(s) can be communicated to the remote computer after and/orduring the computation process. Still further, the remote computer cancommunicate with the QP controller(s) 2320 such that the quantumcomputing process (including any compilation, verification, and QPcontrol procedures) can be remotely controlled by the remote computer2360. In general, the remote computer 2360 communicates with the QPcontroller(s) 2320, compiler/synthesizer 2322, and/or verification tool2323 via communication connections 2350.

In particular embodiments, the environment 2300 can be a cloud computingenvironment, which provides the quantum processing resources of theenvironment 2300 to one or more remote computers (such as remotecomputer 2360) over a suitable network (which can include the internet).

XVI. Concluding Remarks

Having described and illustrated the principles of the disclosedtechnology with reference to the illustrated embodiments, it will berecognized that the illustrated embodiments can be modified inarrangement and detail without departing from such principles. Forinstance, elements of the illustrated embodiments shown in software maybe implemented in hardware and vice-versa. Also, the technologies fromany example can be combined with the technologies described in any oneor more of the other examples. It will be appreciated that proceduresand functions such as those described with reference to the illustratedexamples can be implemented in a single hardware or software module, orseparate modules can be provided. The particular arrangements above areprovided for convenient illustration, and other arrangements can beused.

What is claimed is:
 1. A method of implementing an error correctionprotocol in a quantum computing device, comprising: performing a quantumoperation in a quantum circuit implemented in the quantum computingdevice; and performing a fault-tolerant error correction protocol usingonly a single ancilla qubit and an error-code distance of 3, wherein theperforming the fault-tolerant error correction protocol comprisesrepeating an error syndrome measurement of a flag circuit comprising theancilla qubit until one of the following is satisfied: (a) if thesyndrome s is repeated twice in a row and there were no flags, apply thecorrection min wt(s); and/or (b) if there were no flags and syndromes s₁and s₂ from two consecutive rounds differ, repeat an syndromemeasurement using non-flag circuits yielding syndrome s, apply thecorrection min wt(s).
 2. The method of claim 1, wherein thefault-tolerant error correction protocol performs syndrome measurementsat most three times.
 3. The method of claim 1, wherein the performingthe fault-tolerant error correction protocol comprises repeating anerror syndrome measurement of the ancilla qubit until one of multiplecriteria is satisfied.
 4. The method of claim 3, wherein the multiplecriteria are three criteria.
 5. A method of implementing an errorcorrection protocol in a quantum computing device, comprising:performing a quantum operation in a quantum circuit implemented in thequantum computing device; and performing a fault-tolerant errorcorrection protocol using only two ancilla qubits and an error-codedistance of 5, wherein the performing the fault-tolerant errorcorrection protocol further comprises tracking a number of timesconsecutive measurements are different and a number of times consecutivemeasurements are equal, and wherein the number of times consecutivemeasurements are different is stored in a first counter n_(diff), andwherein the number of times consecutive measurements are equal is storedin a second counter n_(same).
 6. The method of claim 5, wherein, given asequence of consecutive syndrome measurement outcomes s_(k) and s_(k+1),where k and k+1 are index values indicating the consecutive syndromemeasurement outcomes, the first counter and the second counter aremodified according to a set of rules comprising: (a) if n_(diff)=0 ands_(k)≠s_(k+1) by one; (b) if n_(diff) didn't increase in the previousround, and s_(k)≠s_(k+1), increase n_(diff) by one; and/or (c) if a flagoccurred two rounds ago and s_(k)=s_(k+1), increase n_(same) by one. 7.The method of claim 6, wherein the performing the fault-tolerant errorcorrection protocol comprises repeating syndrome measurements using flagcircuits implemented by the two ancilla bits until one of the followingis satisfied: (a) if at any time a syndrome s is repeated 3 times in arow and there were no flags, apply the correction min wt(s); (b) ifn_(diff)=2 and there were no flags, repeat a syndrome using non-flagcircuits yielding syndrome s, apply the correction min wt(s); (c) if anytwo circuits C(g_(i)) and C(g_(j)), where g_(i) and g_(j) are indexvalues indicating the two circuits, have flagged, repeat the syndromemeasurement using non-flag circuits yielding syndrome s, and apply acorrection from the set {tilde over (E)}₂ ²(g_(i), g_(j), s); (d) if anycircuit C(g_(i)) has flagged and n_(diff)=1, repeat a syndrome usingnon-flag circuits yielding syndrome s, and apply a correction from theset {tilde over (E)}₂ ¹(g_(i), s); and/or (e) if any circuit C(g_(i))has flagged, n_(diff)=0 and n_(same)=1, use the measured syndrome s fromthe last round, and apply a correction from the set {tilde over (E)}₂¹(g_(i), s) ∪{tilde over (E)}₂ ²(g_(i), s).
 8. A method of implementingan error correction protocol in a quantum computing device, comprising:performing a quantum operation in a quantum circuit implemented in thequantum computing device; and performing a fault-tolerant errorcorrection protocol using one or more qubits and stabilizer codes of anarbitrary distance, wherein the performing the fault-tolerant errorcorrection protocol further comprises tracking a number of timesconsecutive measurements of the one or more qubits are different and anumber of times consecutive measurements of the one or more qubits areequal.
 9. A method of implementing an error correction protocol in aquantum computing device, comprising: performing a quantum operation ina quantum circuit implemented in the quantum computing device; andperforming a fault-tolerant error correction protocol using one or morequbits and stabilizer codes of an arbitrary distance, wherein theperforming the fault-tolerant error correction protocol furthercomprises tracking a number of times consecutive measurements of the oneor more qubits are different and a number of times consecutivemeasurements of the one or more qubits are equal, and wherein the numberof times consecutive measurements are different is stored in a firstcounter n_(diff), and wherein the number of times consecutivemeasurements are equal is stored in a second counter n_(same).
 10. Themethod of claim 9, wherein, given a sequence of consecutive syndromemeasurement outcomes s_(k) and s_(k+1), where k and k+1 are index valuesindicating the consecutive syndrome measurement outcomes, the firstcounter and the second counter are modified according to a set of rulescomprising: (a) if n_(diff)=0 and s_(k)≠s_(k+1), increase n_(diff) byone; (b) if n_(diff) didn't increase in the previous round, ands_(k)≠s_(k+1), increase n_(diff) by one; and/or (c) if a flag occurredtwo rounds ago and s_(k)=s_(k+1), increase n_(same) by one.
 11. Themethod of claim 10, wherein the performing the fault-tolerant errorcorrection protocol comprises repeating syndrome measurements using flagcircuits implemented by the one or more ancilla bits until one of thefollowing is satisfied: (a) the same syndrome s is repeated t+1 times ina row and there are no flags, apply the correction min wt(s); (b) therewere no flags and n_(diff)=t, repeat the syndrome measurement usingnon-flag circuits yielding the syndrome s, and apply the correction minwt(s).
 12. A quantum computing system configured to perform the errorcorrection method of claim
 9. 13. One or more computer-readable memoryor storage devices storing computer-executable instructions which whenexecuted by a classical computer cause the classical computer toconfigure a quantum computing system to perform the error correctionmethod of claim
 9. 14. A quantum computing system configured to performthe error correction method of claim
 8. 15. One or morecomputer-readable memory or storage devices storing computer-executableinstructions which when executed by a classical computer cause theclassical computer to configure a quantum computing system to performthe error correction method of claim
 8. 16. A quantum computing systemconfigured to perform the error correction method of claim
 1. 17. One ormore computer-readable memory or storage devices storingcomputer-executable instructions which when executed by a classicalcomputer cause the classical computer to configure a quantum computingsystem to perform the error correction method of claim 1.